Stacked NAND Source-Line Layout for Uniform Sheet Resistance
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in making the sheet resistance of source lines in different cell chips uniform, which affects the performance and defect analysis of NAND flash memory devices.
Innovation Solution
The semiconductor memory device configuration includes a specific structure where the lower cell chip has conductive layers and bonding pads that function as backing wires for the source line, allowing for easier matching of sheet resistance with the upper cell chip, and includes simulated shape portions for defect analysis, enhancing accuracy and reducing misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple cell chips are stacked to increase memory capacity, then the memory device can achieve higher storage density, but the sheet resistance of source lines becomes difficult to uniform across different cell chips
Solution Approach 1:
A fourth conductive layer is introduced as an intermediary component to couple bonding pads and electrically connect to the third conductive layer (source line). This intermediate structure facilitates better electrical connection and helps uniformize sheet resistance across stacked cell chips, resolving the contradiction between increased memory capacity and sheet resistance uniformity.
Solution Approach 2:
The patent transitions from a two-dimensional planar connection to a three-dimensional stacked configuration with multiple conductive layers (first, second, third, and fourth conductive layers) at different vertical levels. This dimensional expansion allows for optimized electrical pathways that maintain sheet resistance uniformity while accommodating multiple cell chips for higher memory capacity.
2Ease of manufacture
If conventional bonding pad structures are used in stacked cell chips, then device fabrication is simpler, but defect analysis accuracy and alignment precision deteriorate
Solution Approach 1:
The fourth conductive layer is designed in advance to specifically couple bonding pads before final assembly, creating predetermined alignment references that facilitate both manufacturing and subsequent defect analysis. This preliminary structuring maintains fabrication simplicity while enabling precise defect detection and alignment verification.
3Manufacturing precision
If additional conductive layers and coupling structures are added to uniform sheet resistance, then sheet resistance uniformity improves, but device complexity increases
Solution Approach 1:
The fourth conductive layer serves multiple functions simultaneously: it couples bonding pads, electrically connects to the source line (third conductive layer), provides alignment references, and facilitates defect analysis. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity while achieving sheet resistance uniformity.
Data Source
AI summary
A semiconductor memory device includes a first cell chip and a second cell chip. The first cell chip includes a first stack, a first conductive layer that is used as a first source line, a second conductive layer that is electrically connected to the first conductive layer, and a plurality of first bonding pads. The second cell chip includes a second stack, a third conductive layer that is used as a second source line, a plurality of second bonding pads that are joined to the plurality of first bonding pads, respectively, and a fourth conductive layer that electrically couples the plurality of second bonding pads and is electrically connected to the third conductive layer. The second conductive layer and the fourth conductive layer are electrically connected.