Stacked Nanoribbon Transistors With Independent Source-Drain Isolation
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Solution Overview
Problem
Existing non-planar transistors, such as FinFETs and GAA transistors, face limitations in independently controlling source and drain regions, leading to electrical coupling and reduced functionality in stacked configurations.
Innovation Solution
The development of vertically stacked transistors with independent source or drain regions, achieved through varying spacing and using sacrificial materials, allows for separate control of each transistor, enabling independent contacts and gates, and accommodating transistors with varying numbers and materials of semiconductor regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked transistors are configured with shared source or drain regions, then device density is improved, but electrical isolation and control between transistors deteriorate
Solution Approach 1:
The patent divides the source/drain region into multiple independent segments, where each transistor in the stack has its own separate source or drain contact. This segmentation breaks the electrical coupling between transistors while maintaining vertical stacking, thereby achieving both high density and proper electrical isolation.
Solution Approach 2:
The patent transitions from a two-dimensional planar configuration to a three-dimensional vertical stack with independent contacts. By utilizing the vertical dimension and providing separate access paths for each transistor's source/drain, the design achieves electrical isolation without sacrificing the space efficiency of vertical stacking.
2Ease of manufacture
If all transistors in a stack use the same number and type of semiconductor regions, then manufacturing is simplified, but adaptability and functionality are reduced
Solution Approach 1:
The patent applies different numbers and types of semiconductor regions to different transistors within the same stack, allowing each transistor to be optimized for specific functions. This local differentiation enables diverse transistor configurations (e.g., different channel widths, materials, or doping) while maintaining a unified manufacturing process framework.
Solution Approach 2:
The patent creates a universal stack structure that can accommodate transistors with varying semiconductor region configurations. The same basic fabrication process can produce transistors with different numbers of channels, materials, or geometries, making the stack adaptable to multiple functional requirements simultaneously.
Data Source
AI summary
A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent sources or drained coupled to different nanoribbons or subsets of nanoribbons in the stack. In previous nanoribbon transistors, source/drain regions join the ends of a stack of nanoribbons together, thus electrically shorting the source ends together and the drain ends together. To achieve a stack of semiconductor regions with independent sources or drains, adjacent nanoribbons in the stack may be set at different distances apart, or the source side and drain side may be deposited in separate deposition processes.