Stacked Nanosheet CMOS Layout for Higher Transistor Density
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in increasing transistor density and performance while maintaining efficiency and flexibility in manufacturing processes.
Innovation Solution
The development of stacked nanosheet structures for field effect transistors (FETs) with different configurations at multiple levels, including the use of epitaxial layers and work function metal layers, allows for the creation of complementary metal oxide semiconductor (CMOS) devices with enhanced performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked nanosheet structures with different configurations are formed at multiple levels, then transistor density and performance are improved, but device complexity and manufacturing process difficulty increase
Solution Approach 1:
The semiconductor device is divided into multiple stacked nanosheet structures at different levels (first level and second level), with each level containing independently configured nanosheets. This segmentation allows different device types (nFET, pFET, CMOS) to be formed in different segments, increasing overall transistor density while managing complexity through modular design.
Solution Approach 2:
The patent transitions from planar 2D device arrangement to 3D stacked architecture by forming nanosheet structures at multiple vertical levels. This dimensional change doubles the active density at a given footprint area, achieving higher transistor density without proportionally increasing the manufacturing process complexity.
2Adaptability or versatility
If multiple device types are formed at the same manufacturing level, then manufacturing flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
Different nanosheet configurations are implemented at different locations and levels within the stacked structure. The first nanosheet structure at the first level has a different configuration than the second nanosheet structure at the second level, allowing each region to be optimized for specific device types (nFET, pFET, or CMOS) while maintaining overall manufacturing flexibility.
3Productivity
If non-planar transistor architectures are used, then device density and performance are improved, but manufacturing process complexity increases
Solution Approach 1:
Multiple nanosheet structures are nested vertically in a stacked configuration, with each nanosheet contained within a defined lateral boundary. This nesting approach achieves high device density by utilizing vertical space while maintaining a compact footprint, and the standardized nested structure simplifies the manufacturing process compared to other 3D architectures.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first stacked nanosheet structure and a second stacked nanosheet structure each including a first nanosheet structure formed at a first level and a second nanosheet structure formed at a second level. A configuration of the first stacked nanosheet structure on the first level is different than a configuration of the second stacked nanosheet structure on the first level, or the configuration of the first stacked nanosheet structure on the second level is different than a configuration of the second stacked nanosheet structure on the second level.