Stacked Nanosheet CMOS Crystal Orientation for PFET and NFET
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Solution Overview
Problem
Conventional stacked CMOS devices with single nanosheet stacks having a {100} crystalline surface orientation for both NFET and PFET result in reduced electrical performance of PFET hGAA devices, as they do not optimize the preferred crystalline orientations for each type of transistor.
Innovation Solution
The formation of semiconductor substrates with two vertically stacked nanosheet stacks, each with a different crystalline surface orientation - {100} for NFET and {110} for PFET - separated by a dielectric material, to provide optimal electrical performance for both types of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single nanosheet stack with {100} crystalline surface orientation is used for both NFET and PFET, then the manufacturing process is simplified, but the electrical performance of PFET hGAA devices is reduced
Solution Approach 1:
The patent divides the nanosheet stack into separate regions with different crystalline orientations. Specifically, it creates a first nanosheet stack with {100} orientation for NFET and a second nanosheet stack with {110} orientation for PFET, allowing each transistor type to have its preferred crystal orientation for optimal electrical performance
Solution Approach 2:
The patent applies different crystalline orientations to different local regions of the device structure. The {100} orientation is used in regions where NFET is formed, while {110} orientation is used in regions where PFET is formed, optimizing the electrical characteristics for each transistor type in its specific location
2Reliability
If vertically stacked nanosheet stacks with different crystalline orientations are formed, then the electrical performance of both NFET and PFET is optimized, but the device structure becomes more complex
Solution Approach 1:
The patent utilizes the vertical dimension to accommodate multiple nanosheet stacks with different crystalline orientations. By stacking the {100} oriented nanosheets and {110} oriented nanosheets vertically with dielectric material between them, the device achieves optimal electrical performance for both NFET and PFET while managing the complexity through vertical integration rather than lateral expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance of stacked CMOS devices by ensuring each transistor type has its preferred crystalline orientation, improving the overall performance of the PFET and NFET hGAA devices.
Implementation Method 1
epitaxially growing a first nanosheet stack of alternating nanosheet layers of a sacrificial semiconductor material and a channel semiconductor material on a first semiconductor substrate with a first crystalline surface orientation
Implementation Method 2
depositing a dielectric layer on a top layer of the sacrificial semiconductor material in one of the first nanosheet stack or the second nanosheet stack
Data Source
AI summary
An approach provides a semiconductor structure with a first crystalline surface orientation and a first nanosheet stack on the semiconductor substrate with the first crystalline surface orientation. The semiconductor substrate structure includes a second nanosheet stack with a second crystalline surface orientation above the first nanosheet stack, wherein the first nanosheet stack and the second nanosheet stack are separated by a dielectric material.