Stacked Nanosheet Transistor Structure for Defect-Free Channels

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Solution Overview

Problem

Conventional nanosheet transistor fabrication techniques face challenges in achieving defect-free channels at arbitrary stack heights due to the limited critical thickness of silicon germanium films, leading to performance limitations and reduced computing power per unit area.

Innovation Solution

The method involves forming nanosheet stacks with alternating sacrificial layers, where all initial Si and SiGe layers are treated as sacrificial layers, allowing for the growth of defect-free silicon channels after their removal, thereby maintaining the SiGe layers within the critical thickness threshold without introducing defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional nanosheet transistor fabrication techniques are used to increase stack height, then device density and computing power per unit area are improved, but defects appear in the channel due to exceeding the critical thickness of silicon germanium films

Engineering Contradiction:
Improvedevice densityVSAvoidchannel defect-free quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The nanosheet stack is segmented into multiple independent channels separated by sacrificial layers. Each channel is formed as a discrete nanosheet with controlled thickness below the critical thickness of silicon germanium, allowing the overall stack height to increase while maintaining defect-free individual channels. The segmentation enables scaling to arbitrary stack heights without compromising channel quality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the thickness parameter of the silicon germanium sacrificial layers to be within the critical thickness threshold, preventing defect formation. By controlling the layer thickness parameter and using selective removal processes, defect-free channels are achieved while maintaining arbitrary stack heights through multiple thin-layer repetitions.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the critical thickness of silicon germanium films is exceeded to achieve arbitrary stack heights, then device density is improved, but manufacturing precision is compromised due to defect formation

Engineering Contradiction:
Improvestack heightVSAvoidchannel quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Sacrificial layers are deposited in advance with precise thickness control below the critical thickness threshold. These pre-formed sacrificial layers serve as templates for subsequent channel formation, ensuring that when channels are created by removing the sacrificial material, the resulting channels have the desired dimensions and defect-free quality from the outset.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Silicon germanium sacrificial layers are introduced as intermediary structures that enable arbitrary stack height configuration. These intermediary layers are deposited with controlled thickness, serve as placeholders during fabrication, and are subsequently removed to create the final channel structures. The intermediary approach allows flexible stacking without directly forming thick defect-prone silicon germanium channels.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If silicon germanium layers are made thicker to maintain structural integrity at higher stack heights, then device stability is improved, but defects are introduced into the channel region

Engineering Contradiction:
Improvestructural integrityVSAvoidchannel defect-free quality
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The nanosheet transistor employs a composite structure alternating between silicon channels and silicon germanium sacrificial layers. This composite approach allows the silicon germanium layers to provide structural support and lattice matching at controlled thicknesses below the critical threshold, while the silicon channels provide defect-free conduction paths. The composite material strategy maintains overall structural integrity without introducing defects into the functional channel regions.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of nanosheet transistors with defect-free channels at arbitrary heights, enhancing device performance and increasing computing power per unit area without compromising the number of channels or channel height.

Implementation Method 1

The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS12176416B2Stacked nanosheet transistor with defect free channel
Publication Date: 2024.12.24 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US12176416B2 patent drawing
  • US12176416B2 patent drawing
  • US12176416B2 patent drawing

AI summary

Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having defect free channels. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating first sacrificial layers and second sacrificial layers. One layer of the first sacrificial layers has a greater thickness than the remaining first sacrificial layers. The first sacrificial layers are removed and semiconductor layers are formed on surfaces of the second sacrificial layers. The semiconductor layers include a first set and a second set of semiconductor layers. The second sacrificial layers are removed and an isolation dielectric is formed between the first set and the second set of semiconductor layers.