Stacked Nanosheet Transistor Layout Without Dummy Gates
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Solution Overview
Problem
Conventional semiconductor structures with dummy gate structures increase power consumption and circuit layout dimensions due to unnecessary gate structures between source and drain structures, limiting design flexibility and transistor performance.
Innovation Solution
A semiconductor structure without dummy gate structures, featuring vertically stacked transistors with gate structures only in the upper or lower transistors, and using conductive vias to connect source and drain structures, reducing the number of contact plugs and simplifying wire routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dummy gate structures are included between source and drain structures, then transistor fabrication is simplified, but power consumption increases and circuit layout dimensions increase
Solution Approach 1:
The patent removes dummy gate structures from the transistor design, extracting only the necessary functional gate structures. This elimination of non-essential gates between source and drain structures directly reduces power consumption while maintaining fabrication simplicity through the self-aligned process.
2Ease of manufacture
If dummy gate structures are included between source and drain structures, then transistor fabrication is simplified, but circuit layout dimensions increase
Solution Approach 1:
The patent removes dummy gate structures from the transistor design, extracting only the necessary functional gate structures. This elimination of non-essential gates between source and drain structures directly reduces power consumption while maintaining fabrication simplicity through the self-aligned process.
Solution Approach 2:
The patent transitions from a planar layout with horizontal dummy gates to a vertically stacked transistor architecture. By stacking transistors vertically and using conductive vias for connections, the design reduces the horizontal footprint while maintaining fabrication simplicity through self-alignment.
3Ease of manufacture
If conventional planar transistor layout is used, then manufacturing process is simpler, but design flexibility is limited
Solution Approach 1:
The patent transitions from a planar layout with horizontal dummy gates to a vertically stacked transistor architecture. By stacking transistors vertically and using conductive vias for connections, the design reduces the horizontal footprint while maintaining fabrication simplicity through self-alignment.
Solution Approach 2:
The patent employs selective gate structure placement and material composition in the vertically stacked transistors, allowing different transistor types (e.g., NFET, PFET) to be integrated in a compact vertical arrangement. This dynamic configuration enhances design flexibility for various circuit applications.
Data Source
AI summary
A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.