Stacked Nanosheet FETs with Shared Gates
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving optimal electrostatics and current density per footprint area, particularly in FinFETs, where nanowires and nanosheets offer superior electrostatics but require innovative manufacturing methods to enhance device performance.
Innovation Solution
A method involving the formation of stacked silicon germanium and silicon layers on a semiconductor substrate, patterning, epitaxial source/drain region growth, and replacing silicon germanium layers with gate regions to create a nanosheet or nanowire configuration, enabling improved electrostatics and current density through precise structural manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET structure is used, then manufacturing is relatively simple, but electrostatics control and current density per footprint area are insufficient
Solution Approach 1:
The patent transitions from planar FinFET structure to three-dimensional stacked nanosheet/nanowire configuration, moving the device architecture into the vertical dimension. Multiple active channels are stacked vertically to achieve superior electrostatics control and higher current density per footprint area, directly resolving the contradiction between improved electrostatics and increased device complexity.
Solution Approach 2:
The channel region is segmented into multiple discrete nanosheets or nanowires stacked vertically, with each layer providing an independent conduction path. This segmentation allows for better electrostatic control over each individual channel while collectively achieving higher current density, addressing the trade-off between electrostatics performance and structural complexity.
2Reliability
If nanowire configuration is used, then electrostatics are improved, but current density per footprint area is lower than nanosheets
Solution Approach 1:
The patent employs different geometric configurations (nanosheet vs. nanowire) for different device regions or applications. Nanosheets are used where maximum current density is required, while nanowires are used where superior electrostatics control is the priority. This local optimization allows selection of the appropriate structure based on specific performance requirements.
3Productivity
If stacked nanosheet configuration is used, then current density per footprint area increases, but manufacturing complexity increases
Solution Approach 1:
The semiconductor layers are pre-formed in a stacked configuration using epitaxial growth before any gate or contact fabrication steps. This preliminary formation of the vertical stack simplifies subsequent processing by establishing the three-dimensional architecture early, making the overall manufacturing process more manageable despite the increased device complexity.
Solution Approach 2:
Silicon germanium sacrificial layers are selectively removed from the stacked structure to release individual nanosheets or nanowires. This extraction process creates the final three-dimensional configuration while allowing standard planar processing techniques to be used for gate and contact formation, thereby reducing manufacturing complexity.
4Reliability
If silicon germanium layers are removed and replaced with gates, then device performance is improved, but manufacturing steps increase
Solution Approach 1:
Silicon germanium layers serve as sacrificial intermediary structures during fabrication. These layers are temporarily incorporated into the stack to enable self-aligned gate formation, then selectively removed to release the final device structure. The intermediary SiGe layers simplify the overall manufacturing sequence by providing a template for precise gate positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrostatic control and current density per footprint area, providing a viable alternative to FinFETs by leveraging the superior properties of nanowires and nanosheets in semiconductor devices, particularly for 3D integration and area scaling.
Implementation Method 1
selectively removing the silicon germanium layers from the plurality of patterned stacks
Implementation Method 2
growing a plurality of epitaxial source/drain regions between the plurality of patterned stacks, wherein the epitaxial source/drain regions are grown from exposed sides of the silicon layers
Data Source
AI summary
A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.