Stacked Nanosheet FET Isolation Using Dielectric Layers and Inner Spacers
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Solution Overview
Problem
Forming robust isolation between vertically stacked nanosheet field effect transistors (FETs) is challenging due to issues with thick sacrificial layers and conformal insulator deposition, which can cause electrical shorts and complicate downstream processing.
Innovation Solution
The formation of a nanosheet stack with alternating layers of sacrificial and semiconductor materials, including a thin insulator layer and inner spacers, to create physical and electrical isolation between the upper and lower nanosheet FETs, allowing for the formation of different work function metals and high-k liners for each stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric layers are added between stacked nanosheet FETs to provide isolation, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The patent divides the isolation structure into multiple discrete dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) separated by inner spacers. This segmentation allows each layer to be independently formed and controlled, providing robust electrical isolation while maintaining manageable structural complexity through systematic layering
Solution Approach 2:
Inner spacers are introduced as intermediary structures between the dielectric layers. These spacers serve as mediators that physically separate and electrically isolate the stacked nanosheet FETs, enabling reliable electrical isolation while the modular spacer-dielectric-spracer architecture keeps the overall device complexity controllable
2Reliability
If inner spacers are formed to separate dielectric layers, then electrical isolation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The inner spacers are formed preliminarily before the dielectric layers are deposited. By pre-forming the spacer structures that define the isolation regions, subsequent dielectric layer deposition and patterning can be performed with reference to these established spacer boundaries, reducing alignment precision requirements for later manufacturing steps
Solution Approach 2:
The inner spacers provide localized isolation structures at specific positions between the stacked nanosheet FETs. This local quality approach allows precise electrical isolation to be achieved at critical interfaces while maintaining broader manufacturing tolerances in non-critical regions, thereby reducing overall manufacturing precision requirements
Data Source
AI summary
A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.