Stacked Nanosheet FET Structure for Short-Channel Control
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Solution Overview
Problem
As the semiconductor industry continues to scale down transistor dimensions, there is a need for further improvements in nanosheet FETs to address challenges such as short-channel effects and increased complexity in processing and manufacturing.
Innovation Solution
The semiconductor device structure incorporates a stack of semiconductor layers with alternating first and second semiconductor layers, forming nanosheet channels surrounded by gate electrodes. This structure includes a complementary FET configuration with vertically stacked source and drain regions, utilizing a liner and dielectric material to protect the nanosheet channels during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but short-channel effects and processing complexity increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channels where the gate electrode completely surrounds the channel region. This gate-all-around configuration provides superior electrostatic control over the channel, effectively suppressing short-channel effects that arise from dimensional scaling. The vertical stacking of multiple nanosheets further increases device density without compromising control.
Solution Approach 2:
The gate electrode is positioned to completely surround the nanosheet channel region, creating a nested configuration where the gate envelops the channel from all sides. This nested geometry ensures that the electric field from the gate penetrates uniformly through the channel thickness, providing enhanced control over carrier flow and reducing the impact of drain-induced barrier lowering and short-channel effects.
2Reliability
If nanosheet FET structure is implemented to reduce short-channel effects, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The channel region is segmented into multiple thin nanosheets stacked vertically, each surrounded by the gate electrode. This segmentation allows for better electrostatic control compared to a single thick channel, as the gate can effectively deplete carriers throughout the entire channel volume. The segmented structure also reduces the equivalent oxide thickness, improving sub-threshold current swing and overall device performance.
Solution Approach 2:
The patent changes the geometric parameters of the channel from a planar configuration to a thin-film nanosheet configuration with specific thickness dimensions. By controlling the nanosheet thickness to be sufficiently thin, the gate achieves complete depletion control, resulting in steeper sub-threshold current swing characteristics. This parameter change transforms the device physics to favor improved performance while managing manufacturing complexity.
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.