Stacked Nanosheet GAA Transistor for Low-Leakage Scaling
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuits (ICs) while maintaining performance and efficiency, particularly in the manufacturing of transistors where traditional methods struggle to achieve high density and low leakage.
Innovation Solution
The development of gate all around (GAA) transistor structures, which involve patterning techniques such as double-patterning or multi-patterning processes, and the use of sacrificial layers and spacers to create complex nanosheet structures, allowing for tighter pitches and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional transistor manufacturing methods are used, then the manufacturing process is simple, but the functional density cannot be increased and leakage remains high
Solution Approach 1:
The channel layer is divided into multiple nanosheets stacked vertically, creating multiple independent conduction paths. This segmentation increases functional density while maintaining control over each individual nanosheet, thereby reducing leakage through better gate control
Solution Approach 2:
The gate structure completely surrounds each nanosheet in a nested configuration, with the gate wrapping around the channel material. This all-around gating provides superior electrostatic control compared to traditional planar gates, reducing leakage while maintaining manufacturing feasibility
2Productivity
If geometry size is decreased to increase functional density, then production efficiency increases and costs decrease, but manufacturing precision requirements become more stringent
Solution Approach 1:
The nanosheets are pre-formed and stacked into a complete stack before the gate structure is created. This preliminary stacking allows for better control over the final geometry and reduces the precision requirements during subsequent gate formation processes
Solution Approach 2:
The transistor structure transitions from a two-dimensional planar configuration to a three-dimensional vertically-stacked architecture. This dimensional change allows increased functional density without proportionally increasing manufacturing precision requirements, as vertical stacking can be achieved through conformal deposition processes
Data Source
AI summary
A transistor includes a first conductive type channel layer, a second conductive type channel layer, a gate structure, first source/drain regions and second source/drain regions. The first conductive type channel layer includes a plurality of first nanosheets. The second conductive type channel layer includes a plurality of second nanosheets stacked over the first nanosheets. The gate structure wraps around each of the first nanosheets and the second nanosheets. The first source/drain regions are disposed on opposite sides of the first nanosheets. The second source/drain regions are disposed on opposite sides of the second nanosheets and electrically isolated from the first source/drain regions.