Stacked Nanosheet Transistor Structure for Stronger Gate Control
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving further improvements in nanosheet FETs to address scaling down issues, particularly in enhancing gate control and reducing short-channel effects while maintaining device performance and manufacturing efficiency.
Innovation Solution
The fabrication process involves forming a stack of semiconductor layers with alternating materials of different etch selectivity and oxidation rates, followed by precise etching and deposition to create nanostructure channels surrounded by a gate electrode, utilizing materials like silicon and silicon germanium, and incorporating epitaxial growth of germanium for enhanced channel mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but gate control and short-channel effects deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channel structures with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sides), providing superior electrostatic control and reducing short-channel effects even at scaled dimensions. The nanosheet channel is surrounded by the gate electrode on all sides, creating a wrap-around gate structure that enhances control effectiveness.
Solution Approach 2:
The patent employs composite material structures including alternating layers of silicon and silicon germanium (SiGe). The silicon layers form the active channel regions while SiGe layers provide strain engineering to enhance carrier mobility. This composite approach allows simultaneous optimization of gate control, carrier transport, and manufacturability at scaled dimensions.
2Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the channel region into multiple discrete nanosheets separated by dielectric layers, creating a stacked configuration. This segmentation allows each nanosheet to be independently controlled by the gate and enables parallel processing of multiple channels. The alternating semiconductor/dielectric layer structure facilitates modular fabrication through sequential deposition and etching steps.
Solution Approach 2:
The patent forms the complete alternating stack of semiconductor and dielectric layers before any channel definition or gate formation steps. This preliminary structuring establishes the three-dimensional architecture early in the fabrication process, enabling subsequent self-aligned patterning and reducing the need for complex alignment steps later. The sacrificial layer is also formed in advance to guide subsequent release and nanosheet formation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control and reduces short-channel effects, improving device performance and manufacturing efficiency by leveraging the properties of germanium for strained channels and selective etching processes.
Implementation Method 1
forming a stack of semiconductor layers with alternating materials of different etch selectivity and oxidation rates, followed by precise etching and deposition to create nanostructure channels
Implementation Method 2
incorporating epitaxial growth of germanium for enhanced channel mobility
Implementation Method 3
create nanostructure channels surrounded by a gate electrode, which allows for fuller depletion in the channel region
Data Source
AI summary
Embodiments of the disclosure provide a semiconductor device structure including a first transistor comprising a plurality of first semiconductor layers vertically stacked, each first semiconductor layer being surrounded by a first gate electrode layer, a second transistor disposed over the first transistor, the second transistor comprising a plurality of second semiconductor layers vertically stacked, each second semiconductor layer being surrounded by a second gate electrode layer different from the first gate electrode layer, an isolation layer disposed between a topmost first semiconductor layer of the first transistor and a bottommost second semiconductor layer of the second transistor, the isolation layer comprising a dielectric material, a first source/drain feature in contact with the first semiconductor layers and a portion of the isolation layer, and a second source/drain feature disposed over the first source/drain feature and in contact with the second semiconductor layers and a portion of the isolation layer, wherein the topmost first semiconductor layer and the bottommost second semiconductor layer comprise alkaline elements diffused from a sacrificial layer comprising a semiconductor metal oxide.