Stacked Nanosheet Gate Length Variation in One Transistor Stack
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Solution Overview
Problem
Existing solutions for fabricating nanosheet transistors are not well-suited for integrating devices with different structural properties, leading to increased die area and reduced design flexibility due to the need for separate processing of nanosheet transistor stacks with varying gate lengths.
Innovation Solution
A method for fabricating stacked nanosheet transistors with different gate lengths in a single nanosheet process flow, involving the formation of Si/SiGe superlattice structures with varying gate lengths, epitaxial source/drain regions, and sequential deposition of ALD oxide and metal layers to form gate electrodes, allowing for integration of transistors with different gate lengths in the same stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate processing of different nanosheet transistor stacks is used, then devices with different structural properties can be fabricated, but die area increases and design flexibility is reduced
Solution Approach 1:
The patent merges multiple nanosheet transistor stacks with different gate lengths into a single integrated structure. Different gate lengths are achieved within the same stack by selectively etching SiGe layers at different depths, allowing multiple transistor types to coexist in one compact unit, thereby reducing die area while maintaining design flexibility.
Solution Approach 2:
The patent transitions from lateral arrangement of separate transistor stacks to vertical stacking in the third dimension. By stacking nanosheet transistors vertically with different gate lengths within the same stack, the design achieves high density and flexibility without increasing die area, as the variation in gate length is achieved through vertical etch depth control rather than lateral separation.
2Adaptability or versatility
If separate processing of different nanosheet transistor stacks is used, then devices with different structural properties can be fabricated, but process complexity increases
Solution Approach 1:
The patent segments the gate length definition process into distinct etching stages. First, a common etch process creates initial gate openings. Then, selective additional etching of SiGe layers creates deeper openings for shorter gate length transistors. This segmentation allows different gate lengths to be defined through controlled etch depth variations rather than completely separate processing flows.
Solution Approach 2:
The patent performs preliminary formation of SiGe layers with different thicknesses before the final gate etching process. Thinner SiGe layers are formed in regions where shorter gate lengths are desired. This preliminary action prepares the structure so that a single etch process naturally creates different gate lengths based on the pre-formed layer thicknesses, reducing the need for multiple separate processing sequences.
3Ease of manufacture
If minimal additional processing steps are used, then fabrication cost is reduced, but integration of different gate lengths becomes difficult
Solution Approach 1:
The patent changes the etch depth parameter selectively within the same processing sequence to achieve different gate lengths. By controlling the etch depth to different levels in different regions of the stack, the process creates multiple gate length variations using the same fundamental etching chemistry and equipment, minimizing additional processing steps while maintaining integration capability.
Solution Approach 2:
The patent uses SiGe layers as intermediary sacrificial layers that mediate the gate length definition process. These SiGe layers are selectively removed to different depths to create the desired gate length variations. The SiGe intermediary allows different gate lengths to be achieved through controlled removal rather than requiring separate processing for each transistor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces complexity and cost by minimizing additional processing steps, enabling the integration of nanosheet transistors with different gate lengths in a single process flow, thereby enhancing design flexibility and reducing die area.
Implementation Method 1
sequential deposition of ALD oxide and metal layers to form gate electrodes
Implementation Method 2
epitaxial source/drain regions
Data Source
AI summary
A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.