Stacked Nanosheet Gate Structure With Shaped Internal Spacers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for high-performance and multifunctional semiconductor devices necessitates improved electrical characteristics and reliability, particularly in devices with fin-shaped channels and Gate-All-Around type field effect transistors, where existing technologies face challenges in maintaining device integrity and efficiency due to size reduction.
Innovation Solution
A semiconductor device design featuring distinct internal spacers for each transistor layer, with varying shapes and formation processes, including indented source/drain patterns and gate structures, to enhance channel layer support and reduce crystal defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If planar MOSFET size is reduced to increase integration, then device density improves, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area and drive current without increasing the planar footprint, thereby improving integration density while maintaining operating characteristics through enhanced current drive capability
Solution Approach 2:
The patent implements Gate-All-Around structure where the gate electrode completely surrounds the nanosheet channel in three dimensions. This nested configuration provides maximum gate control over the channel from all directions (top, bottom, and sides), improving carrier mobility and device performance while enabling smaller feature sizes for higher integration
2Reliability
If FinFET with fin-shaped channel is developed to overcome planar MOSFET limitations, then operating characteristics improve, but device structure complexity increases
Solution Approach 1:
The patent divides the channel into multiple discrete nanosheets stacked vertically, with each nanosheet independently surrounded by its own gate structure. This segmentation allows each nanosheet to be optimally controlled and simplifies the manufacturing process by enabling independent formation and tuning of each channel layer, reducing overall structural complexity
3Reliability
If Gate-All-Around type FET with nanosheets is implemented, then carrier mobility and performance improve, but manufacturing process complexity increases
Solution Approach 1:
The patent forms sacrificial layers and internal spacers before creating the final gate and channel structures. These preliminary structures serve as templates and masks that guide subsequent self-aligned fabrication steps, ensuring precise positioning of nanosheets and gates while simplifying the overall manufacturing process through self-alignment
Data Source
AI summary
A semiconductor device may include a substrate including an active pattern, first channel layers spaced apart on the active pattern in a vertical direction, a first gate structure surrounding the first channel layers, first source/drain patterns on both sides of the first gate structure and connected to the first channel layers, first internal spacers between the first gate structure and the first source/drain patterns, second channel layers spaced apart in the vertical direction on the first channel layers, a second gate structure on the first gate structure and surrounding the second channel layers, second source/drain patterns on both sides of the second gate structure and connected to the second channel layers, and second internal spacers between the second gate structure and the second source/drain patterns. The first and second internal spacers may have different shapes. The vertical direction may be perpendicular to an upper surface of the substrate.