Stacked Nanosheet Transistor Layout Without Intermediate Dummy Gates
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Solution Overview
Problem
Conventional semiconductor transistors with lateral arrangements and dummy gate structures face limitations in reducing horizontal dimensions, leading to increased power consumption and circuit layout complexity due to the presence of dummy gate structures.
Innovation Solution
A semiconductor structure with vertically stacked transistors and no dummy gate structures, featuring conductive vias between source/drain structures, simplifying the transmission gate unit and reducing its dimensions and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lateral transistor arrangement with dummy gate structures is used, then transistor functionality is maintained, but horizontal dimension and power consumption increase
Solution Approach 1:
The patent transitions from a conventional lateral (2D) transistor arrangement to a vertical (3D) stacked configuration. Multiple transistor channels are stacked vertically above each other, allowing multiple transistors to occupy a smaller horizontal footprint while maintaining individual gate control through selective connection to different channel portions.
Solution Approach 2:
The shared gate structure is segmented into different functional regions that can be selectively connected to control different channels. The gate is divided into first and second portions, where the first portion controls a first channel and the second portion controls a second channel, enabling independent control despite physical sharing.
2Use of energy by moving object
If dummy gate structures are present in transmission gate units, then transistor operation is ensured, but power consumption and layout complexity increase
Solution Approach 1:
The patent removes dummy gate structures from the transmission gate configuration by using selective gate connections. Instead of requiring dummy gates to maintain transistor operation, the design selectively connects gate portions to active channels through conductive elements, eliminating unnecessary structures that consume power and increase complexity.
Solution Approach 2:
The shared gate structure serves multiple functions by controlling multiple channels simultaneously. A single gate structure replaces what would traditionally require multiple separate gates and dummy gates, reducing overall device complexity while maintaining full functionality across different transmission states.
3Area of stationary object
If vertically stacked transistors are implemented without dummy gate structures, then transmission gate unit dimension is reduced, but gate control complexity increases
Solution Approach 1:
The patent implements a nested structure where conductive elements are positioned between source/drain regions and gate structures. These conductive elements selectively connect gate portions to channels, creating a compact nested arrangement that reduces overall area while managing control complexity through hierarchical organization of conductive paths.
Data Source
AI summary
A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.