Stacked Nanosheet Transistor Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Three-dimensional transistor structures experience electrical vulnerabilities such as parasitic capacitance between the contact metal and gate metal, which reduces device performance.
Innovation Solution
A nanosheet transistor device with a transistor stack comprising a lower tri-gate nanosheet transistor and an upper tri-gate nanosheet transistor, where the upper nanosheet transistor has a different width and gate width than the lower one, and a gate-free region adjacent the source/drain contact to reduce parasitic capacitance by removing a portion of the gate electrode material closest to the source/drain contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional transistor structures are used to increase transistor density, then transistor density is improved, but parasitic capacitance between contact metal and gate metal increases
Solution Approach 1:
The gate electrode is segmented into multiple sections along the channel length, with different sections having different widths. This segmentation allows the gate to maintain adequate width for control while reducing the width near contacts, thereby reducing parasitic capacitance while preserving transistor density benefits
Solution Approach 2:
Different sections of the gate electrode are given different local properties - wider sections over the channel for strong control and narrower sections near contacts for reduced parasitic capacitance. This local differentiation resolves the contradiction between needing wide gates for control and narrow gates near contacts for low parasitic capacitance
2Object-generated harmful factors
If gate electrode material is removed to reduce parasitic capacitance, then parasitic capacitance is reduced, but gate control capability may be weakened
Solution Approach 1:
The gate is divided into segments where only the portions near contacts are narrowed or removed, while the central channel portions maintain full width for adequate control. This selective segmentation reduces parasitic capacitance without compromising gate control capability
Solution Approach 2:
The gate electrode exhibits local quality variations - full width for strong control in channel regions and reduced width near contacts for low parasitic capacitance. This local differentiation ensures control capability is maintained where needed while reducing parasitic effects where appropriate
Data Source
AI summary
Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.