Stacked Nanosheet ROM With Distinct Threshold Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in efficiently integrating read-only memory (ROM) into stacked nanosheet field effect transistors (FETs) while maintaining device performance and reducing transistor dimensions.
Innovation Solution
The approach involves forming a semiconductor device with two stacked nanosheet memory cells, each with alternating layers of different work function metals and semiconductor channel materials, allowing for distinct threshold voltages to be achieved by using different work function metals for each memory cell, enabling simultaneous fabrication and control of memory states during device production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If stacked nanosheet FETs are used to reduce transistor dimensions, then device footprint is reduced, but integration of memory cells becomes more complex
Solution Approach 1:
The device is segmented into distinct lower and upper nanosheet stacks, each functioning as an independent memory cell. The lower nanosheet stack contains first work function metal layers, while the upper nanosheet stack contains second work function metal layers, allowing separate control and simplifying the integration of multiple memory cells in a compact footprint.
Solution Approach 2:
Different work function metals are applied locally to different nanosheet stacks to achieve distinct threshold voltages. The first work function metal in the lower stack provides one threshold voltage characteristic, while the second work function metal in the upper stack provides a different threshold voltage characteristic, enabling differentiated memory cell behavior within the same device structure.
2Manufacturing precision
If different work function metals are used for different memory cells, then distinct threshold voltages are achieved, but manufacturing process complexity increases
Solution Approach 1:
The work function metal layers are deposited and patterned during the initial fabrication stages, before final device assembly. By establishing the different work function metal configurations early in the manufacturing process, the threshold voltage characteristics are predetermined, simplifying subsequent processing steps and reducing overall manufacturing complexity.
Solution Approach 2:
The same basic nanosheet stack structure and fabrication processes are used for both lower and upper memory cells, providing universality. The only differentiation is the work function metal composition, which can be controlled through standard deposition and patterning techniques, allowing multi-functional memory cells to be manufactured using largely the same process toolkit.
3Quantity of substance
If multiple nanosheet stacks are vertically stacked, then memory density is increased, but manufacturing precision requirements increase
Solution Approach 1:
Multiple nanosheet stacks are merged into a single vertically integrated structure sharing common substrate and support infrastructure. The lower and upper nanosheet stacks are combined in the vertical dimension, allowing memory density to increase while utilizing the same manufacturing platform and process steps for both stacks, thereby reducing the relative precision burden.
Data Source
AI summary
A semiconductor device including a first nanosheet stack of two memory cells including a lower nanosheet stack on a substrate including alternating layers of a first work function metal and a semiconductor channel material vertically aligned and stacked one on top of another, and an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material vertically aligned and stacked one on top of another, the upper nanosheet stack vertically aligned and stacked on the lower nanosheet stack, where a first memory cell of the two memory cells including the lower nanosheet stack includes a first threshold voltage and a second memory cell of the two memory cells including the upper nanosheet stack includes a second threshold voltage, where the first threshold voltage is different than the second threshold voltage. Forming a semiconductor device including a first nanosheet stack of two memory cells.