Stacked Nanosheet pFET-nFET Shared Drain Architecture
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Solution Overview
Problem
As semiconductor devices continue to shrink, the implementation of stacked nanosheets offers a reduced footprint, but existing methods face challenges in achieving efficient gate control and increasing integration density due to increased resistance in the source/drain region, leading to performance limitations.
Innovation Solution
The method involves forming vertically stacked three-dimensional nanosheet semiconductor devices with pFET and nFET transistors, where the drains of both are electrically connected, and utilizing a top-down approach to grow epitaxial layers and isolate the transistors, allowing for better gate control and increased density by reducing the overall area size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar semiconductor devices are used, then device footprint is larger, but manufacturing and integration are simpler
Solution Approach 1:
The patent transitions from conventional planar (2D) semiconductor devices to vertically stacked three-dimensional nanosheet devices. Multiple nanosheets are stacked in the vertical dimension to increase integration density and reduce footprint while maintaining electrical performance. The gate structure wraps around the stacked nanosheets in a surround-gate configuration, utilizing the third dimension to improve gate control and reduce device area.
Solution Approach 2:
The patent implements a nested structure where the gate electrode surrounds the stacked nanosheets in a wrap-around configuration. The gate structure is positioned both above and below the nanosheet stack, with gate dielectric layers enclosing the active channel regions. This nested arrangement maximizes gate control over the channel while minimizing the lateral footprint of the device.
2Productivity
If stacked nanosheets are implemented to reduce footprint, then integration density increases, but source/drain resistance increases leading to performance limitations
Solution Approach 1:
The patent merges multiple nanosheets into a vertically stacked configuration to increase integration density. Multiple active channels are combined in the vertical dimension, allowing higher transistor density per unit area. The shared gate structure controls all nanosheets simultaneously, improving overall device performance while maintaining compact footprint.
Solution Approach 2:
The patent applies selective doping to different regions of the stacked nanosheet structure. Source and drain regions are selectively doped in specific nanosheets to optimize carrier concentration and reduce resistance. The gate dielectric layers are engineered with different properties at different locations to optimize electrical characteristics while managing resistance in the source/drain regions.
3Area of moving object
If vertically stacked pFET and nFET are formed with shared drain, then area is reduced by up to half, but fabrication process complexity increases
Solution Approach 1:
The patent combines pFET and nFET devices in a vertically stacked configuration with shared drain and gate structures. Complementary transistors are integrated in the same vertical column, sharing common elements such as the drain region and gate electrode. This merging of complementary devices reduces the lateral area required for CMOS circuits by approximately 50% compared to conventional planar layouts.
Solution Approach 2:
The shared gate structure serves multiple functions by controlling both pFET and nFET channels simultaneously. The common drain region acts as both the drain for one transistor and the source for the other in the complementary pair. This multi-functionality reduces the number of separate structures required, simplifying the overall device architecture despite the complex fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significant reduction of the semiconductor device area by up to half, enabling higher integration density and lower costs per transistor while maintaining performance by improving gate control and current conduction.
Implementation Method 1
growing a first epitaxial layer on the source and drain
Implementation Method 2
forming three-dimensional nanosheet stacks including alternating silicon layers and silicon germanium layers on a substrate
Data Source
AI summary
A method for fabricating a stacked nanosheet semiconductor device includes forming nanosheet stacks including alternating silicon layers and silicon germanium layers on a substrate. The method includes patterning a gate structure on the nanosheet stacks and forming a source and drain on the stacks. The method further includes growing a first epitaxial layer on the source and drain. The method includes etching an interlayer dielectric on the first epitaxial layer. The method includes etching a portion of the first epitaxial layer forming a channel and growing a second epitaxial layer and etching a portion of the interlayer etching a portion of the first liner, forming a pFET. The method includes forming an nFET. The method includes the pFET and the nFET being disposed adjacent to one another vertically and a drain of the pFET and a drain of the nFET being electrically connected.