Stacked Nanosheet MBCFET Layout for SRAM Current Control
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density, particularly in static random-access memory (SRAM) applications, due to limitations in scaling and control over current.
Innovation Solution
The semiconductor device incorporates multi-bridge channel field-effect transistors (MBCFETs) with a specific architecture that includes multiple layers of nanosheets and stack separation layers, along with gate electrodes and source/drain regions, to enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling techniques are used to increase integration density, then device density improves, but control over current deteriorates and short channel effect increases
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet structures with multiple channels stacked vertically. This dimensional change allows current to flow through multiple parallel paths (increasing integration density) while each individual nanosheet maintains excellent gate control, thereby resolving the contradiction between density and control
Solution Approach 2:
The channel region is segmented into multiple discrete nanosheets stacked vertically, with each nanosheet acting as an independent current path. The gate electrode wraps around each nanosheet individually, providing segmented control over each channel segment. This segmentation allows high integration density through multiple channels while maintaining precise current control over each segment
2Reliability
If gate length is increased to improve current control, then short channel effect is mitigated, but device scaling is restricted
Solution Approach 1:
The invention moves from one-dimensional planar gates to three-dimensional wrapped gates that surround the nanosheet channels vertically and horizontally. This dimensional change in gate structure provides superior electrostatic control without requiring increased gate length, allowing continued scaling while mitigating short channel effects
Solution Approach 2:
The gate electrode is nested around the nanosheet channel in a wrap-around configuration, with the gate completely surrounding the channel region. This nested geometry provides maximum gate control over the channel with minimal gate length, effectively mitigating short channel effects while enabling continued device scaling
Data Source
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AI summary
A semiconductor device includes a lower interlayer insulating layer, an insulating pattern extending in a first horizontal direction, a first plurality of lower nanosheets and a second plurality of lower nanosheets, a first plurality of middle nanosheets and a second plurality of middle nanosheets, a first plurality of upper nanosheets and a second plurality of upper nanosheets. The semiconductor device includes a first stack separation layer, a second stack separation layer, a first gate electrode, a second gate electrode, a first middle source/drain region, a second middle source/drain region, and a middle source/drain contact. The middle source/drain contact is electrically connected to the first and second middle source/drain regions and penetrates the lower interlayer insulating layer and the insulating pattern in a vertical direction. An upper surface of the middle source/drain contact is formed lower than a bottom surface of a lowermost nanosheet of the first plurality of upper nanosheets.