Stacked Nanosheet Transistor Source/Drain Structure for Strain Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration, effective channel strain control, and improved electrical reliability as scaling technologies advance.
Innovation Solution
The semiconductor device incorporates a fin-type pattern with a first and second active pattern, a gate electrode surrounding these patterns, and source/drain patterns with specific film configurations to enhance integration and strain control, while using a fence film and fin-type protrusions for improved electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-gate transistor with fin-shaped or nanowire-shaped silicon body is used, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The source/drain structure is segmented into multiple regions with different materials (semiconductor material, first doped semiconductor material, second doped semiconductor material) to enable independent optimization of different functional zones, thereby managing manufacturing complexity while achieving high integration density
Solution Approach 2:
Different regions of the source/drain structure are assigned different material properties and doping concentrations to achieve optimal local performance, allowing complex functionality to be realized through localized variations rather than uniform complex structures
2Quantity of substance
If three-dimensional stacked semiconductor device is used, then integration density is improved, but channel strain control becomes more difficult
Solution Approach 1:
The patent applies different doping concentrations and material compositions at specific locations within the source/drain structure to generate controlled strain in the channel region, enabling precise strain management in three-dimensional stacked devices
Solution Approach 2:
The patent modifies physical parameters such as doping concentration, material composition, and structural dimensions in the source/drain regions to induce and control strain effects in the channel, thereby achieving improved carrier mobility while maintaining three-dimensional stacking
3Reliability
If source/drain pattern with multiple films is used, then electrical reliability is improved, but device complexity increases
Solution Approach 1:
The source/drain structure employs composite materials including semiconductor material, doped semiconductor material, and different dopant types (p-type and n-type) to achieve superior electrical reliability through material synergies, while the systematic arrangement keeps complexity manageable
Data Source
AI summary
A semiconductor device includes a first active pattern including first sheets spaced apart in a first direction perpendicular to a surface of a substrate, a second active pattern on the first active pattern and including second sheets spaced apart in the first direction, a first source/drain pattern connected to the first active pattern in a second direction, a second source/drain pattern on the first source/drain pattern and connected to the second active pattern in the second direction, and a gate electrode extending in a third direction and extending around the first and the second active patterns. The first source/drain pattern includes a first film along an inner surface of a recess where the first source/drain pattern is disposed and a second film on the first film and filling the recess. On a cross-section including the first and third directions, the recess decreases in width with decreasing distance to the substrate.