Stacked Nanosheet Transistor Structure for Semiconductor Miniaturization
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Solution Overview
Problem
Existing semiconductor technologies have not adequately addressed the challenge of further miniaturization in semiconductor devices.
Innovation Solution
A semiconductor device structure is designed with stacked transistors and nanosheets arranged between insulating walls, utilizing specific semiconductor layers and gate electrodes with insulating films to enhance miniaturization, and a manufacturing method involving epitaxial growth and etching processes to form nanosheet structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional planar transistor structures are used, then manufacturing is simpler, but device miniaturization is limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to 3D vertical structures by stacking multiple semiconductor layers (first, second, third, and fourth semiconductor layers) with corresponding gate electrodes above and below each layer. This vertical stacking enables multiple transistors to occupy a smaller planar footprint while maintaining functional integrity through three-dimensional spatial arrangement.
Solution Approach 2:
The patent implements nested structures by placing gate electrodes, insulating films, and semiconductor layers within each other in vertical stacks. Each transistor layer is nested within a common structure that includes gate electrodes positioned above and below the semiconductor layers, with insulating walls separating adjacent transistors, creating a compact nested arrangement that reduces overall device volume.
2Manufacturing precision
If transistor density is increased through stacking, then miniaturization is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the transistor structure into discrete segmented layers including first and second semiconductor layers, third and fourth semiconductor layers, with corresponding gate electrodes and insulating films between each layer. This segmentation into standardized repeating units simplifies the manufacturing process by enabling modular fabrication where each layer can be processed independently with consistent precision requirements, rather than requiring complex monolithic structures.
Solution Approach 2:
The patent employs epitaxial growth processes with controlled parameters to form semiconductor layers with precise thicknesses and compositions. By adjusting growth parameters such as temperature, pressure, and precursor flow rates during epitaxial formation, the patent achieves accurate layer thickness control and material composition to meet the precision requirements of high-density stacked transistor fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables further miniaturization of semiconductor devices while maintaining functional integrity, allowing for improved performance and efficiency in semiconductor circuits.
Implementation Method 1
a manufacturing method involving epitaxial growth and etching processes to form nanosheet structures
Data Source
AI summary
A semiconductor device includes, above a substrate, a first layer with, on both sides in a direction, first regions; a second layer above the first layer with, on both sides in the direction, second regions above the first regions; a third layer, third regions, a fourth layer, and fourth regions, corresponding to the first layer, first regions, second layer, and second regions, respectively, the third layer being side by side with the first layer in another direction, the fourth layer being side by side with the second layer in the other direction; first and second gate electrodes above the first and second layers and the third and fourth layers, and having gate insulating films between these gate electrodes and these layers; and an insulating wall extending in the direction with both side surfaces contacted by the first and second layers and the third and fourth layers, respectively.