T-Shaped Stacked Nanosheet Transistors for Higher Drive Current
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Solution Overview
Problem
The drive current in nanowire transistors is limited due to the reduction of channel width for greater device density in semiconductor integrated circuits, hindering further scaling down and efficiency improvements.
Innovation Solution
The implementation of a semiconductor device structure with T-shaped stacked nanosheet transistors, where the second semiconductor layers are laterally recessed, providing additional conductive area for effective control of nanosheet channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channel width is reduced to increase device density, then device density is improved, but drive current deteriorates
Solution Approach 1:
The patent transitions from conventional planar transistors to three-dimensional nanosheet transistors with vertically stacked channels. By stacking multiple thin semiconductor layers vertically, the effective channel width is increased in the vertical dimension while maintaining a small lateral footprint, thus improving drive current without sacrificing device density. The nanosheet structure comprises multiple thin semiconductor layers (e.g., silicon, germanium, or III-V materials) stacked vertically with each layer contributing to the total channel conduction area.
Solution Approach 2:
The patent employs composite material structures where different semiconductor materials are stacked together to form the nanosheet channels. This includes using materials with different bandgaps, carrier mobilities, and etch selectivities (e.g., Si/SiGe, GaAs/AlAs) to optimize both electrical performance and manufacturability. The composite structure allows for selective removal of sacrificial layers and precise control of channel properties while maintaining high device density.
2Length of moving object
If channel length is reduced to improve scaling, then device scaling is improved, but drive current deteriorates
Solution Approach 1:
The patent compensates for reduced channel length by increasing the effective channel width through vertical stacking of multiple nanosheet layers. The total drive current is enhanced by the cumulative contribution of multiple parallel channels stacked vertically, effectively decoupling the drive current from the lateral channel length constraint. This allows aggressive scaling of channel length while maintaining or improving drive current through the vertical dimension.
Solution Approach 2:
The channel is segmented into multiple discrete nanosheet layers stacked vertically, each acting as an independent conduction path. This segmentation allows the total channel width to be distributed across multiple thin layers rather than requiring a single thick layer, enabling better control of short-channel effects while maintaining high drive current through the combined effect of multiple segments.
3Speed
If nanowire transistor structure is used to improve carrier mobility, then carrier mobility is improved, but drive current reaches a limit due to reduced channel width
Solution Approach 1:
The patent extends the successful nanowire concept by stacking multiple nanosheet layers vertically to create a multi-channel structure. This maintains the high carrier mobility advantage of nanoscale channels while multiplying the effective channel width by the number of stacked layers, thereby breaking the drive current limit imposed by single-nanowire geometries.
Solution Approach 2:
The patent uses composite semiconductor material stacks where high-mobility materials (e.g., Ge, GaAs, InGaAs) are combined with sacrificial materials (e.g., SiGe, AlAs) that have different etch rates. This composite approach enables selective removal of sacrificial layers to form suspended nanosheet channels with high carrier mobility while the multi-layer structure provides the necessary total channel width for high drive current.
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor device structure including a substrate, a first channel layer disposed over the substrate, wherein the first channel layer has a first width; a second channel layer disposed between the first channel layer and the substrate, wherein the second channel layer has a second width less than the first width, and the second channel layer has a first surface in contact with the first channel layer and a second surface in contact with the substrate. The structure also includes a third channel layer disposed over the first channel layer, a gate dielectric layer disposed on the first channel layer, the second channel layer, and the third channel layer. The structure further includes a gate electrode layer disposed on the gate dielectric layer, the gate electrode layer separating the first channel layer and the third channel layer.