Stacked Nanostructure Transistors With Separate Gates for Dense Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating multiple electronic components efficiently while maintaining performance and density, particularly in forming stacked transistors with separate control over lower and upper gate structures.
Innovation Solution
The development of stacked transistors with multiple vertically stacked nanostructure-FETs, including lower and upper semiconductor nanostructures, separated by gate dielectrics and electrodes, and isolated by source/drain regions, allowing for a compact footprint and improved device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple electronic components are integrated into a given area by reducing minimum feature size, then integration density is improved, but manufacturing complexity and additional problems arise
Solution Approach 1:
The patent transitions from planar transistor integration to three-dimensional stacked transistor integration. Multiple transistors are stacked vertically along the channel length direction, enabling multiple components to occupy a smaller footprint area by utilizing the vertical dimension. This dimensional change allows higher integration density without proportionally increasing manufacturing complexity, as the stacking approach provides a systematic method for multi-transistor integration.
2Reliability
If stacked transistors are formed with separate control over lower and upper gate structures, then device performance and control are improved, but structural complexity increases
Solution Approach 1:
The transistor structure is segmented into distinct lower and upper gate regions with separate control capabilities. The channel is divided such that the lower gate controls a first portion of the channel and the upper gate controls a second portion. This segmentation enables independent voltage control of different channel sections, improving device performance and enabling new functionality while maintaining a systematic structural organization.
Solution Approach 2:
The patent implements a nested structure where the lower gate and upper gate are positioned at different vertical levels, with the lower gate structure containing the lower gate electrode and dielectric, and the upper gate structure containing the upper gate electrode and dielectric. These nested gate structures allow separate control of different channel portions while being integrated within a single transistor footprint.
Data Source
AI summary
Various embodiments include stacked transistors and methods of forming stacked transistors. In an embodiment, a device includes: a first nanostructure; a second nanostructure above the first nanostructure; a first gate structure extending along a top surface and a bottom surface of the first nanostructure; and a second gate structure extending along a top surface and a bottom surface of the second nanostructure. The first gate structure is disposed at a first side of the first nanostructure and a first side of the second nanostructure. The second gate structure is disposed at a second side of the first nanostructure and a second side of the second nanostructure. The second side of the first nanostructure is opposite the first side of the first nanostructure. The second side of the second nanostructure opposite the first side of the second nanostructure.