Stacked Nanowire Transistors With Backside Power Access
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in lithographic processes, particularly in maintaining the critical dimension and spacing between features, leading to trade-offs in device performance and power delivery networks, which affects the efficiency and area usage in semiconductor fabrication.
Innovation Solution
Implementing a backside power delivery network for integrated circuit structures, allowing for wider metal lines and reduced power network resistance, and using a 4 poly pitch (4pp) wide bitcell design without the need for split gates or gate contact networks, thereby simplifying the fabrication process and improving SRAM bitcell area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional front-side power delivery networks are used, then the power delivery structure is simple, but the metal lines must be narrow which increases power network resistance
Solution Approach 1:
The patent implements backside power delivery networks that route power lines through the substrate backside, transitioning from a single-plane (front-side only) configuration to a three-dimensional configuration. This allows power lines to be wider and shorter on the backside, reducing resistance while maintaining overall structural simplicity through vertical separation of power and signal routing planes.
2Area of stationary object
If standard bitcell designs are used, then the fabrication process is straightforward, but the area efficiency is lower due to required gate contact networks
Solution Approach 1:
The patent eliminates the gate contact network from the bitcell structure by implementing a 4 poly pitch wide bitcell design where gates are directly accessible from the bitline without requiring separate contact structures. This extraction of the gate contact network reduces bitcell area and simplifies the fabrication process by removing additional masking and patterning steps.
3Productivity
If feature dimensions are scaled down to increase density, then more devices fit on chip, but the spacing between features becomes constrained limiting further scaling
Solution Approach 1:
The patent utilizes vertical stacking of transistors and routing layers to achieve higher device density without further constraining lateral feature spacing. By moving to three-dimensional device architectures and multi-layer routing, the design accommodates increased functionality while maintaining adequate lithographic spacing constraints.
Data Source
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AI summary
Structures having stacked transistors with backside access are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer including first, second, third and fourth stacks of nanowires and corresponding first, second, third and fourth overlying gate lines, and the device layer including first, second, third, fourth and fifth source or drain structures and corresponding overlying trench contacts alternating with the stacks of nanowires and the overlying gate lines, and one or more metallization layers above the device layer. A backside structure includes a backside via connection coupled to a bottom portion of the third source or drain structure, the bottom portion of the third source or drain structure isolated from a top portion of the third source or drain structure.