Stacked Nanowire Fabrication via Oxidation and Etching
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Solution Overview
Problem
Existing methods for fabricating stacked nanowires from multiple-material fins face challenges due to differing etch rates, resulting in inconsistent fin widths, which hinders the scalability and density of integrated circuits.
Innovation Solution
The method involves etching vertical fins from a single-material substrate and forming spacers at vertically separated positions, followed by oxidation to create nanowires, ensuring consistent width and density through the use of conformal silicon nitride films and directional reactive ion etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple-material fins are used to fabricate stacked nanowires, then the fabrication process can proceed, but inconsistent fin widths result due to differing etch rates
Solution Approach 1:
The patent uses single-material fins (silicon) instead of multiple-material fins, ensuring uniform etch rates throughout the fin structure. This homogeneity in material composition eliminates the width inconsistency problem that arises when etching through layers of different materials with different etch rates.
Solution Approach 2:
The patent segments the fin structure into multiple vertical sections, each containing a nanowire, separated by spacer regions. This segmentation allows independent formation and control of each nanowire segment, ensuring consistent dimensions across all nanowires even though they are part of a continuous fin structure.
2Productivity
If vertically stacked nanowires are formed, then transistor density increases, but fabrication complexity increases
Solution Approach 1:
The patent transitions from planar transistor architecture to vertically stacked nanowire architecture, utilizing the vertical dimension to increase transistor density. Multiple nanowires are stacked vertically within a single footprint area, effectively using the third dimension (height) to pack more transistors into the same chip area.
Solution Approach 2:
The patent forms spacers at predetermined vertical positions along the fin structure before the oxidation step. This preliminary placement of spacers defines the exact locations where nanowires will subsequently form, ensuring precise vertical positioning and spacing of nanowires without requiring complex post-formation alignment processes.
3Measurement precision
If spacers are formed at vertically separated positions, then nanowire positioning precision improves, but process steps increase
Solution Approach 1:
The patent uses spacers as intermediary structures that are temporarily formed to define nanowire positions, then removed after serving their positioning function. These spacers act as sacrificial templates that guide the oxidation process to form nanowires at precise locations, after which the spacers themselves are etched away, leaving only the cleanly positioned nanowires.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of vertically stacked nanowires with consistent dimensions, enhancing the scalability and density of integrated circuits by maintaining uniformity across the substrate.
Implementation Method 1
oxidizing to form the nanowires at the vertically separated positions of the fin
Implementation Method 2
directional reactive ion etching
Data Source
AI summary
A method of fabricating stacked nanowire for a transistor gate and a stacked nanowire device are described. The method includes etching a fin as a vertical structure from a substrate and forming two or more pairs of spacers at vertically separated positions of the fin. The method also includes oxidizing to form the nanowires at the vertically separated positions of the fin.