Stacked Nanowire Transistors With Region-Specific Gate Widths
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Solution Overview
Problem
Existing nanowire device fabrication techniques face challenges in efficiently forming gate-all-around devices with varying numbers of vertically arranged nanowire channels, which affects the effective gate width and performance characteristics of the devices.
Innovation Solution
A method involving the formation of a stack of nanosheets on a substrate, followed by the creation of nanosheet fins and sacrificial gates, allows for the formation of gate stacks around multiple vertically arranged nanowire channels, enabling devices with different performance characteristics to be fabricated on a single wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If nanowire devices are formed using conventional fabrication techniques, then devices with uniform gate width are produced, but the ability to create devices with varying effective gate widths on a single wafer is limited
Solution Approach 1:
The fabrication process segments the wafer into different regions (first region and second region) with distinct nanosheet fin configurations. The first region receives a first number of etch releases while the second region receives a second number of etch releases, creating nanowire devices with different effective gate widths from a common nanosheet stack structure.
Solution Approach 2:
The patent utilizes the vertical stacking dimension by forming multiple nanosheet fins stacked vertically. By controlling the number of nanosheet fins in the vertical stack and the number of etch releases applied to different regions, the effective gate width can be varied without changing the lateral footprint of the devices.
2Reliability
If multiple nanosheet fins are stacked vertically to increase effective gate width, then device performance is improved, but the fabrication process becomes more complex
Solution Approach 1:
The nanosheet stacks are formed preliminarily across the entire wafer before any region-specific processing. The alternating layers of first and second nanosheet materials are deposited and patterned into vertical fins in advance, allowing subsequent selective etching to create different device configurations from the same pre-formed stack structure.
Solution Approach 2:
Different regions of the wafer are treated with different numbers of etch releases applied to specific nanosheet fins. The first region receives a first number of etch releases while the second region receives a second number, creating local variations in the number of nanowire channels while maintaining a uniform overall process approach.
3Adaptability or versatility
If different numbers of nanowire channels are formed in different regions, then diverse performance characteristics are achieved, but the manufacturing process requires additional steps
Solution Approach 1:
The common nanosheet stack structure serves multiple functions: it provides the vertical channel formation, the template for selective etching, and the basis for both types of nanowire devices. This universal structure allows the same fabrication steps to produce different device configurations, improving productivity despite the need for region-specific processing.
Solution Approach 2:
The fabrication process uses periodic alternating layers of first and second nanosheet materials that are deposited in sequence. This periodic structure enables selective removal of specific layers through targeted etching processes, allowing different numbers of nanowire channels to be formed in different regions while maintaining process efficiency.
Data Source
AI summary
A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.