Stacked Nanowire Structure Manufacturing via Segmented Etching
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Solution Overview
Problem
The semiconductor industry faces challenges in forming high aspect ratio fin or stacked nanowire structures for FinFETs and GAA FETs, particularly in controlling deep etching processes as device sizes shrink to sub-10-15 nm technology nodes, leading to difficulties in achieving precise control over the formation of these structures.
Innovation Solution
A method for manufacturing GAA FETs and stacked channel FETs involves forming alternating stacks of semiconductor layers with different materials, patterning them into fin structures, and then etching the substrate to create mesa structures, followed by the formation of nanowire structures and gate dielectric layers, which allows for improved control over the device architecture and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional deep etching processes are used to form high aspect ratio fin structures, then device density can be increased, but control precision over the etching process deteriorates
Solution Approach 1:
The patent segments the continuous etching process into multiple discrete stages with intermediate treatments. The etching is divided into first and second etching operations with different parameters, and includes intermediate steps such as depositing sacrificial layers and performing annealing treatments. This segmentation allows better control over the deep etching process to achieve high aspect ratio structures with precise dimensional control.
Solution Approach 2:
The patent applies preliminary actions before the main etching process by forming sacrificial semiconductor layers and performing pre-etching preparations. These preliminary structures guide the subsequent etching process and enable better control over the final fin structure dimensions, resolving the contradiction between achieving high device density and maintaining etching precision.
2Length of moving object
If transistor dimensions are scaled down to sub 10-15 nm nodes, then device performance is improved, but fabrication control becomes more difficult
Solution Approach 1:
The patent employs parameter changes by varying etching conditions, temperature, and material composition at different stages of the process. The etching parameters are adjusted based on the specific dimensions being formed, enabling precise control over sub-10-15 nm transistor features. Temperature control during annealing and etching parameter optimization allow fabrication control to be maintained even as dimensions are scaled down.
3Quantity of substance
If high aspect ratio structures are formed, then device density increases, but etching process complexity increases
Solution Approach 1:
The patent introduces intermediary sacrificial semiconductor layers that act as mediators during the etching process. These intermediate structures simplify the overall process by providing templates and control mechanisms that reduce the complexity of forming high aspect ratio structures. The sacrificial layers are removed after serving their guiding function, leaving the desired fin structures with controlled dimensions.
Data Source
AI summary
A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate.