Stacked Nanowire Transistors with Selective Etching
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Solution Overview
Problem
Existing methods for making superimposed transistors are not adaptable to all types of FET transistors, particularly GAAFET, and do not allow for independent control of individual transistors, limiting their performance and integration density.
Innovation Solution
A method involving distinct etching steps to form channels and source/drain regions independently for each transistor, allowing for different dimensions, materials, and dopings, enabling independent control and integration of multiple transistors with varying geometries and types, such as nFET and pFET, on a substrate with high density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If existing methods for making superimposed transistors are used, then transistor stacking is achieved, but independent control of individual transistors is not possible
Solution Approach 1:
The patent divides the nanowire stack into multiple independently controllable segments by performing selective etching at different depths. Each etching step exposes a specific nanowire or group of nanowires to form separate channels, allowing each transistor to be controlled independently through its own gate electrode while maintaining the stacked configuration.
2Adaptability or versatility
If existing methods for making superimposed transistors are used, then transistor integration is achieved, but adaptability to different FET types (especially GAAFET) is limited
Solution Approach 1:
The patent employs a dynamic, multi-step etching process that can be adjusted to create different transistor configurations. By controlling the etching depth, duration, and selectivity in each step, the same base process can be adapted to form various FET types including GAAFET, planar FET, and other configurations, making the manufacturing method highly versatile.
3Power
If multiple nanowires are superimposed to increase current, then channel current capacity is improved, but stray capacitances increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration, allowing multiple nanowires to be vertically superimposed. This vertical stacking increases the effective channel width and current capacity while maintaining compact footprint. The independent etching steps allow for optimized spacing and gating structures that minimize stray capacitance between adjacent nanowires in the stack.
Data Source
AI summary
An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.