Stacked 3D Nanowire Inverter With Shared Hybrid Gate
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Solution Overview
Problem
Existing inverter layouts for high-density thick gate SoC applications require separate gate electrodes and distinct footprints for N-type and P-type transistors, leading to area-intensive configurations and increased routing complexity in the back end of line (BEOL).
Innovation Solution
Implementing a single gated nanowire inverter with stacked transistors, where N-type and P-type transistors share a hybrid gate electrode, reducing the footprint on the substrate and eliminating the need for additional BEOL routing by vertically stacking the transistors and sharing a gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate gate electrodes are used for N-type and P-type transistors, then each transistor can be optimized for its specific conductivity type, but the substrate footprint increases and routing complexity in BEOL increases
Solution Approach 1:
The patent merges the gate electrodes of N-type and P-type transistors into a single shared gate electrode structure. This is achieved by forming a common gate electrode that electrically connects to both transistor types, eliminating the need for separate gate electrodes while maintaining optimized performance for each conductivity type through appropriate work function material selection.
Solution Approach 2:
The single gate electrode structure serves multiple functions by simultaneously controlling both N-type and P-type transistors. The gate electrode is designed with multi-functionality to provide optimized gate control for different transistor types through selective contact regions and appropriate work function materials, reducing substrate footprint while maintaining reliability.
2Reliability
If separate gate electrodes are used for N-type and P-type transistors, then each transistor can be optimized for its specific conductivity type, but routing complexity in BEOL increases
Solution Approach 1:
The patent merges the gate electrode structures and their associated routing into a single integrated configuration. By combining the gate electrodes and sharing common routing paths in the BEOL, the design eliminates redundant routing layers and vias that would otherwise be required for separate gate electrodes, thereby reducing routing complexity while maintaining transistor performance optimization.
3Reliability
If channel lengths are increased to 100 nm or larger, then transistor performance can be maintained, but the area occupied by each transistor increases
Solution Approach 1:
The patent transitions from planar transistor布局 to a three-dimensional stacked configuration where N-type and P-type transistors are vertically stacked above each other. This dimensional change allows the transistors to share the same lateral footprint while maintaining adequate channel lengths for performance, effectively moving the design into the vertical dimension to reduce overall area occupation.
Data Source
AI summary
Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.