Vertically Stacked Nanowire TFET for High Driving Current
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Solution Overview
Problem
Tunneling field-effect transistors (TFETs) face limitations in driving current, which affects their operating speed, and attempts to increase current through shorter gates or larger channels either lead to short channel effects or contradict the trend of miniaturization and higher integration in semiconductor chips.
Innovation Solution
A tunneling field-effect transistor with vertically stacked nanowires and a fabrication method involving a substrate, source, drain, gate insulation layer, and gate structure, where the substrate is an intrinsic substrate, and the nanowires are formed using anisotropic and isotropic etching, with impurity ion injection and hydrogen annealing to enhance current without altering gate length or channel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate length is shortened to increase driving current, then the driving current increases, but short channel effect occurs
Solution Approach 1:
The patent transitions from a planar 2D channel structure to a vertically stacked 3D nanowire structure. Multiple nanowires are stacked in the vertical direction to increase the effective channel area and driving current, while maintaining a sufficiently long gate length in the horizontal plane to avoid short channel effects. This dimensional transition allows simultaneous optimization of both driving current and device reliability.
Solution Approach 2:
The channel is segmented into multiple independent nanowires stacked vertically. Each nanowire acts as an independent current path, and the total driving current is the sum of currents through all nanowires. This segmentation increases the effective channel area without requiring a larger planar footprint, thus maintaining compatibility with standard gate lengths and avoiding short channel effects.
2Power
If the channel area is increased to increase driving current, then the driving current increases, but the transistor size increases reducing integration density
Solution Approach 1:
The patent utilizes the vertical dimension by stacking multiple nanowires to increase the effective channel area. This vertical expansion allows the transistor to achieve higher driving current without increasing the planar footprint (length and width), thereby maintaining high integration density while improving electrical performance.
Solution Approach 2:
Multiple nanowires are nested vertically within a compact structure, with each nanowire contained within the gate region. This nesting arrangement maximizes the channel area within a minimal footprint, allowing high driving current through multiple parallel paths while maintaining small transistor dimensions for high integration density.
3Power
If multiple nanowires are vertically stacked to increase channel area, then driving current increases, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming sacrificial nanowires, depositing gate materials, removing sacrificial structures, and forming source/drain regions. Each stage is independently optimized and can be performed using standard semiconductor processing techniques, making the complex multi-nanowire structure manufacturable through systematic process decomposition.
Solution Approach 2:
Sacrificial nanowires are introduced as intermediary structures during fabrication. These temporary structures enable precise positioning and formation of the final nanowire channels through a sequence of deposition, etching, and release steps. The sacrificial nanowires mediate the complex transformation from simple precursor structures to the final multi-nanowire device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher driving current without short channel effects, stabilizes the gate electrode formation, and reduces surface roughness, improving device performance and integration density.
Implementation Method 1
patterning a channel on the substrate by using anisotropic etching
Implementation Method 2
forming a nanowire on the substrate by using isotropic etching
Implementation Method 3
a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected
Implementation Method 4
reducing a surface roughness of the nanowire by hydrogen annealing
Data Source
AI summary
A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).