Stacked Nanowire TFT Structure for Short-Channel Control
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Solution Overview
Problem
As transistors are scaled down to critical dimensions below 100 nm, particularly below 50 nm, they experience undesirable short channel effects (SCE), increased current leakage, reduced contact resistance, and degraded subthreshold swing characteristics, limiting current handling capacity and switching speed.
Innovation Solution
The implementation of stacked nanowire thin film transistors with a gate-all-around (GAA) architecture, where a high-k dielectric layer and a metal gate layer wrap around each nanowire body, enhancing electrostatic control and increasing the gate surface contact area, along with nanowire bodies made of materials like indium gallium zinc oxide (IGZO) and group III-V semiconductor materials, to mitigate SCE and reduce external contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is scaled down to below 100 nm, then transistor density increases, but short channel effects worsen
Solution Approach 1:
The gate structure completely surrounds the nanowire channel in a nested configuration, with the gate electrode wrapping around the nanowire from all sides. This three-dimensional gate-all-around structure provides superior electrostatic control over the channel compared to planar gates, enabling effective suppression of short channel effects while maintaining scaled dimensions
Solution Approach 2:
The invention transitions from two-dimensional planar transistor structures to three-dimensional nanowire structures with gate-all-around configuration. This dimensional change allows the gate to control the channel from multiple directions (top, bottom, and sides), significantly improving electrostatic control and reducing short channel effects at scaled dimensions
2Productivity
If transistor size is scaled down to below 50 nm, then transistor density increases, but current leakage increases
Solution Approach 1:
The gate electrode completely surrounds the nanowire channel in a nested configuration, providing electrostatic control from all directions. This three-dimensional gate-all-around structure effectively suppresses short channel effects and reduces current leakage by maintaining strong electric field control over the entire channel perimeter
Solution Approach 2:
The transition to three-dimensional nanowire structures with gate-all-around configuration enables the gate to control the channel from multiple directions, significantly improving electrostatic control and reducing current leakage at scaled dimensions below 50 nm
3Ease of manufacture
If conventional TFT structures are used, then manufacturing is simpler, but contact resistance is higher
Solution Approach 1:
The source and drain regions are merged with the nanowire body to form a continuous semiconductor structure, eliminating the need for separate contact formation processes. This integration reduces contact resistance by creating direct ohmic contacts between the metal electrodes and the nanowire channel
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces short channel effects, improves electrical conduction, and increases transistor density, enabling faster switching speeds and enhanced current handling capacity.
Implementation Method 1
a gate-all-around (GAA) architecture, in which the gate structure includes a high-k dielectric layer and a metal gate layer wrapped around each of the stacked nanowire bodies to provide improved electrostatic control
Implementation Method 2
The resulting increased gate surface contact area also provides improved electrical conduction
Data Source
AI summary
Thin film transistor structures and processes are disclosed that include stacked nanowire bodies to mitigate undesirable short channel effects, which can occur as gate lengths scale down to sub-100 nanometer (nm) dimensions, and to reduce external contact resistance. In an example embodiment, the disclosed structures employ a gate-all-around architecture, in which the gate stack (including a high-k dielectric layer) wraps around each of the stacked channel region nanowires (or nanoribbons) to provide improved electrostatic control. The resulting increased gate surface contact area also provides improved conduction. Additionally, these thin film structures can be stacked with relatively small spacing (e.g., 1 to 20 nm) between nanowire bodies to increase integrated circuit transistor density. In some embodiments, the nanowire body may have a thickness in the range of 1 to 20 nm and a length in the range of 5 to 100 nm.