Stacked Nanowire N/P Transistor Architecture for Higher Integration Density
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Solution Overview
Problem
The existing arrangement of P-type and N-type transistors with stacked semi-conducting rods poses a size problem due to the need for adjacent placement, which limits integration density and increases chip size.
Innovation Solution
A device with stacked transistors is designed, where each transistor has a channel formed by semi-conducting rods, with distinct source and drain blocks and independent surrounding gates, allowing for increased integration density and reduced size while maintaining high current levels and low leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P-type and N-type transistors are positioned next to each other with stacked semi-conducting rods, then the channel structure provides proper electrostatic control and low leakage, but the chip size increases and integration density decreases
Solution Approach 1:
The patent merges P-type and N-type transistors into a single integrated structure where they share common semi-conducting rods and source/drain blocks. This combination allows both transistor types to coexist in a compact arrangement, reducing the overall chip area while maintaining proper electrostatic control through the surrounding gate configuration.
Solution Approach 2:
The patent implements a nested arrangement where P-type and N-type transistors are interleaved within the same vertical stack. The transistors share common semi-conducting rods and source/drain blocks, with each transistor type nested within the structure of the other, maximizing space utilization and reducing chip size.
2Reliability
If P-type and N-type transistors are positioned next to each other with stacked semi-conducting rods, then the channel structure maintains proper electrostatic control, but the integration density is limited
Solution Approach 1:
The patent combines multiple transistor functions into a single integrated stack, where P-type and N-type transistors share common semi-conducting rods and source/drain blocks. This merging increases the number of transistors per unit area, thereby improving integration density while maintaining electrostatic control through the surrounding gate design.
Solution Approach 2:
The patent transitions from a planar transistor arrangement to a vertical stacked configuration. By stacking semi-conducting rods vertically and interleaving P-type and N-type transistors in the vertical dimension, the design achieves higher integration density by utilizing the third dimension (height) rather than only the planar area.
3Productivity
If transistors are stacked with distinct source and drain blocks, then the current level per unit area increases, but the device complexity increases
Solution Approach 1:
The patent merges source and drain blocks between P-type and N-type transistors, creating shared blocks that serve multiple functions. This reduction in redundant components simplifies the overall device structure while maintaining high current levels through the stacked semi-conducting rod configuration.
Solution Approach 2:
The patent implements universal source and drain blocks that serve multiple transistor types simultaneously. The shared source/drain blocks perform multiple functions for both P-type and N-type transistors, reducing device complexity while maintaining high current density through the vertical stack architecture.
Data Source
AI summary
A device with stacked transistors includes a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, and a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods. The source block of the second transistor is distinct from the source and drain block of the second transistor, and the drain block of the second transistor is distinct from the drain and source blocks of the second transistor.