Vertically Stacked Nanowire Transistors for RF Linearity
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Solution Overview
Problem
Conventional transistors face challenges in achieving high linearity, especially at low power and room temperature, due to mobility degradation and bias-dependent source/drain resistance, which leads to distortion in RF communications.
Innovation Solution
A field effect transistor structure with a stack of vertically separated channel nanowires, each with different thicknesses, dopant concentrations, or semiconductor materials, isolated from the substrate and connected by a gate electrode, which maintains transconductance flatness over a wide bias range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used, then device simplicity is maintained, but linearity deteriorates due to mobility degradation and bias-dependent source/drain resistance
Solution Approach 1:
The channel is segmented into multiple vertically stacked nanowires (n=2-20) with different thicknesses, dopant concentrations, or semiconductor materials. Each nanowire contributes differently to the overall transconductance characteristic, enabling the composite structure to maintain flatter transconductance over a wider bias range and improve linearity while managing the complexity through modular stacking
Solution Approach 2:
Different regions of the channel (individual nanowires) are assigned different local properties including varying thicknesses, dopant concentrations, and semiconductor materials. This local differentiation allows each nanowire to compensate for the non-linearities of others, collectively achieving superior linearity performance that cannot be obtained with uniform channel structures
Solution Approach 3:
The channel comprises composite structures with at least two different semiconductor materials, dopant concentrations, or thicknesses stacked vertically. This composite approach enables tuning of the overall transconductance characteristic by combining materials and structures with complementary properties, achieving high linearity at low power and room temperature
2Reliability
If high linearity is achieved through circuit level integration of discrete devices, then linearity improves, but resource consumption and device footprint increase
Solution Approach 1:
Multiple nanowire channels are merged into a single vertically stacked structure that functions as one integrated transistor. This consolidation achieves high linearity performance that would otherwise require multiple discrete devices and circuit-level integration, thereby reducing the device footprint and resource consumption while maintaining superior linearity characteristics
3Use of energy by moving object
If low power operation is implemented, then energy consumption decreases, but achieving high linearity becomes extremely difficult at room temperature
Solution Approach 1:
The invention changes key physical parameters of the channel including using different semiconductor materials with appropriate bandgaps, varying dopant concentrations, and adjusting nanowire thicknesses. These parameter modifications enable the device to achieve high linearity at low power and room temperature by optimizing the transconductance characteristics without requiring high operating voltages or temperatures
Data Source
AI summary
A field effect transistor structure comprises a source and a drain on a substrate, and a stack of n vertically separated channel nanowires isolated from the substrate and connecting the source and the drain, where n is an integer and 2≦n≦20. The channel nanowires collectively comprise at least two different thicknesses and/or at least two different dopant concentrations and/or at least two different semiconductor materials.