Stacked Nanowire Transistors With Tuned Geometry and Planar Topography
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Solution Overview
Problem
It is challenging to manufacture multiple stacked nanowire transistors with different characteristics in a single integrated circuit, which is necessary for various functions such as input/output, core processing, and memory storage, due to the complexity of scaling down semiconductor processes.
Innovation Solution
The process involves forming a semiconductor stack with alternating layers of different materials, patterning, and selectively etching to create elongated semiconductor features that can be used as nanowires, allowing for the formation of transistors with varying characteristics by using epitaxial growth and etching techniques to tune the dimensions and shapes of these features, and forming gate structures that wrap around the nanowires to enable different transistor functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple stacked nanowire transistors with different characteristics are manufactured in a single integrated circuit, then transistor functionality for different operations (input/output, core processing, memory storage) is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into multiple regions, each containing semiconductor stacks with different characteristics. By segmenting the circuit into distinct functional zones with customized nanowire transistors, the system achieves diverse transistor functionality while managing manufacturing complexity through modular regional fabrication
Solution Approach 2:
The patent implements local quality by creating semiconductor stacks with different characteristics in different regions of the integrated circuit. Each region is tailored with specific nanowire dimensions, materials, and configurations to optimize performance for particular operations such as input/output, core processing, or memory storage functions
2Productivity
If semiconductor scaling down process is applied, then production efficiency is improved and costs are lowered, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional stacked nanowire transistors, utilizing the vertical dimension to increase functional density. This dimensional change allows multiple nanowires to be stacked vertically, improving production efficiency and reducing chip area while managing manufacturing complexity through established epitaxial growth techniques
3Adaptability or versatility
If elongated semiconductor features are formed with varying dimensions and shapes, then transistor customization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs parameter changes by varying the dimensions, shapes, and material compositions of elongated semiconductor features through controlled epitaxial growth processes. By adjusting growth parameters such as temperature, pressure, and precursor flow rates, the system achieves transistor customization while maintaining manufacturing precision through well-established semiconductor fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the customization of transistors within an integrated circuit, enabling efficient production of stacked nanowire transistors with varying characteristics, such as different thicknesses and pitches, that can be used for specific functions while maintaining a planar surface, simplifying subsequent layer formation and improving transistor performance.
Implementation Method 1
forming a semiconductor stack with alternating layers of different materials, patterning, and selectively etching to create elongated semiconductor features that can be used as nanowires, allowing for the formation of transistors with varying characteristics by using epitaxial growth and etching techniques
Data Source
AI summary
A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.