Stacked Neural Core Interconnects for Low-Latency AI Dies
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Solution Overview
Problem
Conventional neural network circuits face challenges with high latency, long interconnects, and large footprints due to complex addressing systems and limited signal types, particularly in routing spiking signals, and require significant area for dedicated wire connections.
Innovation Solution
The neural computing dies feature vertically stacked neural core regions with conductive pathways for inter-core interconnects, allowing direct output from one core to serve as input for the next, simplifying routing and accommodating value-based signals, thereby reducing latency and footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional neural network circuits use complex addressing systems and dedicated wire connections for routing, then signal routing capability is improved, but interconnect length and device footprint increase significantly
Solution Approach 1:
The patent transitions from planar (2D) neural core arrangements to a three-dimensional stacked architecture. Multiple neural cores are vertically stacked with inter-core interconnect regions positioned between them, enabling direct vertical signal pathways. This dimensional change dramatically reduces interconnect length while maintaining full routing capability between all neural cores.
2Adaptability or versatility
If conventional neural network circuits use distributed neural cores in a single plane with complex addressing systems, then routing flexibility is improved, but latency increases
Solution Approach 1:
By stacking neural cores vertically and positioning inter-core interconnect regions between them, the patent creates direct short-range signal pathways. This eliminates the need for long lateral routes required in planar configurations, dramatically reducing signal propagation time and latency while preserving routing flexibility through the vertical dimension.
3Reliability
If conventional neural network circuits use dedicated wire connections between coplanar neural cores, then signal transmission reliability is improved, but area footprint increases
Solution Approach 1:
The stacked architecture with inter-core interconnect regions positioned between neural cores enables direct vertical signal transmission. This three-dimensional arrangement provides reliable dedicated pathways while occupying significantly less planar area compared to coplanar configurations that require extensive lateral wire routing.
Solution Approach 2:
The patent merges multiple neural cores and their interconnect structures into a compact stacked assembly. The inter-core interconnect regions are integrated between the neural cores rather than being separate lateral connections, consolidating the overall structure and reducing total footprint while maintaining signal transmission reliability.
Data Source
AI summary
Disclosed herein are neural computing dies with stacked neural core regions as well as related methods and assemblies. In some embodiments, a neural computing die may include: a first neural core region; a second neural core region; and an inter-core interconnect region in a volume between the first neural core region and the second neural core region, wherein the inter-core interconnect region includes a conductive pathway between the first neural core region and the second neural core region, and the conductive pathway includes a conductive via.