Stacked Neuron Transistor Structure for High-Density Neuromorphic Computing
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Solution Overview
Problem
Traditional neuron devices face challenges with low power efficiency and reliability, particularly in supporting the high demands of large-scale parallel computing for deep learning applications, as they rely on classic Von Neumann architecture and require improvements in neuromorphic designs.
Innovation Solution
A stacked neuron device structure comprising a substrate with peripheral circuits, a barrier layer, and a neuron transistor array with a semiconductor channel, modulation stack, and gate array, where the neuron transistors are controlled by peripheral circuits to modulate the weighting floating gate, enabling efficient weighting and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional neuron devices use classic Von Neumann architecture, then device structure is simpler, but power efficiency is low and reliability is poor
Solution Approach 1:
The patent transitions from planar 2D transistor architecture to 3D vertically stacked architecture. Multiple neuron transistors are stacked in the vertical dimension, allowing parallel processing while maintaining compact footprint. This dimensional change enables improved power efficiency through better resource utilization without proportionally increasing device complexity
Solution Approach 2:
The neuron device is segmented into distinct functional layers: input layer, weighting layer, summation layer, and output layer. Each layer is implemented as a separate transistor stage in the vertical stack, with floating gates providing independent control. This segmentation enables modular design that improves power efficiency while keeping each segment relatively simple
2Productivity
If neuron devices increase integration for parallel computing, then computing capability improves, but power consumption increases and reliability decreases
Solution Approach 1:
Multiple functional components are merged into a single vertically integrated stack: input transistors, weighting transistors with floating gates, summation nodes, and output transistors are combined in one compact structure. This merging achieves high parallel computing capability through vertical stacking while improving reliability by reducing the total number of interconnections and external components
Solution Approach 2:
The patent implements a nested structure where floating gates are embedded within the transistor stack, and multiple neuron units are nested vertically. Each neuron transistor contains nested functional elements (gate, channel, floating gate, substrate) that work together. This nesting achieves high integration for parallel computing while maintaining reliability through compact, self-contained units
3Speed
If neuron devices use traditional transistor structure, then manufacturing process is simpler, but response speed is slower and carrier mobility is lower
Solution Approach 1:
The patent changes key structural parameters of the transistor: introducing floating gates with adjustable potentials, creating vertically stacked configurations, and modifying channel dimensions. These parameter changes improve carrier mobility and response speed by optimizing electric field distribution and reducing transit time, while remaining compatible with standard semiconductor fabrication processes
Solution Approach 2:
The neuron transistor employs composite material structures including semiconductor channels, insulating layers, conductive floating gates, and substrate materials. This composite structure optimizes carrier transport properties and electrical characteristics for faster response, while using materials that are compatible with existing manufacturing processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the integration and response speed of neuron devices by using a junctionless transistor structure, reducing process complexity and improving carrier mobility, thereby addressing the limitations of traditional neuron devices in power efficiency and reliability.
Implementation Method 1
The summing process of the neuron transistor on the gate can use the voltage mode of the capacitive coupling effect
Data Source
AI summary
This invention provides a stacked neuron device structure and a manufacturing method thereof. The device comprises: a substrate with peripheral circuits in the substrate; a barrier layer; a neuron transistor array, comprising a plurality of neuron transistors arranged in an array, wherein the transistor comprises a semiconductor channel, a modulation stack, and a gate array; the two ends of the semiconductor channel are respectively connected to peripheral circuits, and the peripheral circuit is used to control the gating or closing of the corresponding neuron transistor. The first dielectric layer, the weighting floating gate layer and the second dielectric layer are stacked in this order. The gate array is located on the modulation stack and is used to modulate the potential of the weighting floating gate to realize the weighting of the weight floating gate. The invention realizes a structure and manufacturing method of a junctionless neuron device arranged in an array on a plane and vertically stacked in the longitudinal direction. The on and off of each neuron transistor is controlled by the peripheral circuit in the substrate, which greatly improves the packing density of the neuron devices.