Vertically Stacked nFET pFET with Independent Work Function Control
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Solution Overview
Problem
Existing semiconductor devices with vertically stacked nFETs and pFETs using nanosheet technology lack independent work function control for nFETs and pFETs, limiting their performance beyond the 7 nm technology node.
Innovation Solution
A semiconductor structure with vertically stacked nFETs and pFETs featuring Si channel material nanosheets and independent work function metal gates for nFETs and pFETs, where pFETs have a p-type work function metal gate and nFETs have an n-type work function metal gate, formed through a method involving sacrificial SiGe nanosheets and epitaxial growth processes to create suspended nanosheets and gate cavities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically stacked nFETs and pFETs with nanosheet technology are used, then area scaling and electrostatics control are improved, but independent work function control for nFETs and pFETs is lost
Solution Approach 1:
The gate structure is segmented into separate first and second gate structures, where the first gate structure controls the nFET and the second gate structure controls the pFET. This segmentation allows independent work function control for each transistor type while maintaining the vertically stacked nanosheet configuration, thereby resolving the contradiction between area scaling and independent work function control.
Solution Approach 2:
Different work function metals are applied to different regions: a first work function metal is applied to the first gate structure for nFET control, while a second work function metal is applied to the second gate structure for pFET control. This local differentiation enables independent work function tuning for each transistor type within the compact stacked architecture.
2Productivity
If vertically stacked nFETs and pFETs are implemented, then device density and area scaling are improved, but device complexity increases
Solution Approach 1:
The method combines the formation of multiple gate structures and work function metals into a unified process sequence. Gate structures are formed simultaneously, followed by selective removal and work function metal deposition, which simplifies the overall manufacturing process while achieving high device density through vertical stacking.
Solution Approach 2:
The sacrificial nanosheets are formed and positioned in advance before the gate structures are created. This preliminary action establishes the vertical stacking geometry early in the process, enabling subsequent gate formation and work function metal deposition to proceed efficiently without requiring complex repositioning or restructuring operations.
3Reliability
If nanosheet technology is used for vertical stacking, then electrostatics control is improved, but manufacturing precision requirements increase
Solution Approach 1:
Sacrificial nanosheets serve as intermediary structures that guide the formation of the final device architecture. These sacrificial elements are formed with standard precision, then used as templates to position gate structures and work function metals accurately. After completing the functional structure formation, the sacrificial nanosheets are removed, having fulfilled their positioning role without requiring ultra-high precision in the final device layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables independent control of work functions for nFETs and pFETs, enhancing electrostatics control and area scaling, thereby improving device performance beyond the 7 nm technology node.
Implementation Method 1
The sacrificial gate structure and each recessed sacrificial SiGe nanosheet of the first and second nanosheet stacks are then removed to suspend each Si channel material nanosheet and to provide a gate cavity
Implementation Method 2
A gate dielectric material is then formed in the gate cavity and on physically exposed surfaces of each suspended Si channel material nanosheet
Implementation Method 3
A p-type work function metal is then formed on the gate dielectric material. Next, the p-type work function metal is removed from the gate cavity present below and above each suspended Si channel material nanosheet of the second nanosheet stack. An n-type work function metal is formed in the gate cavity present between and above each suspended Si channel material nanosheet of the second nanosheet stack
Data Source
AI summary
A semiconductor structure is provided that includes a pFET device including a first functional gate structure containing at least a p-type work function metal and present on physically exposed surfaces, and between, each Si channel material nanosheet of a first set of vertically stacked and suspended Si channel material nanosheets. The structure further includes an nFET device stacked vertically above the pFET device. The nFET device includes a second functional gate structure containing at least an n-type work function metal present on physically exposed surfaces, and between, each Si channel material nanosheet of a second set of vertically stacked and suspended Si channel material nanosheets.