Stacked III-Nitride Transistor and Diode Package
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Solution Overview
Problem
Conventional packaging methods for combining III-nitride transistors with silicon diodes increase parasitic inductance, resistance, thermal dissipation requirements, form factor, and manufacturing cost due to side-by-side placement on common substrates, which negates the benefits of high-efficiency III-nitride transistors.
Innovation Solution
A stacked package design where a silicon diode is directly attached to the source electrode of a III-nitride transistor, reducing parasitic inductance and resistance, improving thermal dissipation, and minimizing form factor and manufacturing costs by using solder, conductive adhesive, or conductive tape for mechanical and electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If discrete components are placed side-by-side on a common substrate, then manufacturing and assembly are simplified, but parasitic inductance and resistance increase
Solution Approach 1:
The patent merges the transistor and diode into a single integrated device structure where the diode is formed within the transistor package. The diode anode is connected to the transistor source region and the diode cathode is connected to the transistor drain region, creating a combined structure that eliminates the need for separate discrete components and their interconnections, thereby reducing parasitic inductance while maintaining manufacturing simplicity.
Solution Approach 2:
The diode structure is nested within the transistor structure by forming the diode active region within or adjacent to the transistor source/drain regions. This nesting approach allows both devices to share common substrate real estate and electrical pathways, reducing the overall package size and minimizing the length of current paths which reduces parasitic inductance.
2Adaptability or versatility
If discrete components are placed side-by-side on a common substrate, then individual device optimization is maintained, but package form factor increases
Solution Approach 1:
By combining the diode and transistor into a single integrated device, the patent achieves both device optimization and compact form factor. The shared structure allows each device to be optimized for its specific function while occupying minimal space through the integrated architecture rather than requiring separate discrete component areas.
Solution Approach 2:
The patent transitions from a planar side-by-side arrangement to a three-dimensional integrated structure where the diode is formed within the vertical depth of the transistor structure. This dimensional change allows both devices to coexist in a compact volume, reducing the package form factor while maintaining individual device performance.
3Device complexity
If discrete components are placed side-by-side on a common substrate, then routing is simplified, but thermal dissipation requirements increase
Solution Approach 1:
The integrated device structure merges the thermal pathways of the transistor and diode, allowing heat from both devices to be dissipated through common thermal vias and heat sinks. This shared thermal management architecture reduces the overall thermal dissipation requirements compared to separate discrete components while maintaining simplified routing.
Data Source
AI summary
One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.