Stacked NMOS Gate Structure for Compact Bandgap Reference Circuits
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Solution Overview
Problem
Conventional bipolar junction transistors (BJTs) occupy a large area and are high power-consuming, making them non-competitive for shrinkage in semiconductor devices.
Innovation Solution
The use of flip-gate and negative-gate NMOS transistors with specific metal gate structures and epitaxy configurations, along with a current mirror circuit, to enhance the reference voltage and reduce the driving voltage threshold, thereby optimizing semiconductor device area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional BJT is used for bandgap reference circuit, then reference voltage can be achieved, but area occupied is larger and power consumption is higher
Solution Approach 1:
The patent changes the fundamental device type from BJT to NMOS transistor, altering the operating parameters and mechanism. The NMOS transistor uses field-effect operation instead of bipolar junction operation, achieving reference voltage generation through different physical parameters (threshold voltage characteristics) while reducing power consumption and area
Solution Approach 2:
The patent employs standard NMOS transistor technology which is more readily available and requires less resource-intensive manufacturing compared to BJT. The NMOS structure uses simpler fabrication processes and occupies less silicon real estate, making it a more efficient replacement for BJT in bandgap reference circuits
2Area of stationary object
If conventional BJT is used for bandgap reference circuit, then reference voltage can be achieved, but device area is larger
Solution Approach 1:
The patent changes the fundamental device type from BJT to NMOS transistor, altering the operating parameters and mechanism. The NMOS transistor uses field-effect operation instead of bipolar junction operation, achieving reference voltage generation through different physical parameters (threshold voltage characteristics) while reducing power consumption and area
Solution Approach 2:
The patent employs standard NMOS transistor technology which is more readily available and requires less resource-intensive manufacturing compared to BJT. The NMOS structure uses simpler fabrication processes and occupies less silicon real estate, making it a more efficient replacement for BJT in bandgap reference circuits
3Ease of operation
If flip-gate and negative-gate NMOS transistors are used, then driving voltage threshold is reduced and reference voltage is increased, but device structure becomes more complex
Solution Approach 1:
The patent applies different gate structures (flip-gate and negative-gate configurations) to specific transistors within the circuit based on their functional requirements. The negative-gate NMOS transistor is used where threshold voltage reduction is needed, while flip-gate configurations are applied where reference voltage enhancement is required. This localized application of specialized structures optimizes performance without unnecessarily complicating the entire device
Solution Approach 2:
The patent combines multiple transistor types (flip-gate NMOS and negative-gate NMOS) with different metal gate structures within a single bandgap reference circuit. This composite approach leverages the complementary strengths of each transistor type to achieve both reduced threshold voltage and enhanced reference voltage output
Data Source
AI summary
A semiconductor device includes a first transistor and a second transistor. The first transistor includes a plurality of first active channels and a first metal gate. The first active channels are stacked to each other. The first metal gate is formed on the first active channels. The first metal gate includes a plurality of first P-metal layers and a first N-metal layer stacked to the first N-metal layer. The second transistor includes a plurality of second active channels and a second metal gate. The second active channels are stacked to each other. The second metal gate is formed on the second active channels, wherein the second metal gate includes a second N-metal layer.