Stacked NMOS and PMOS Transistor Thickness for Carrier Mobility
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Solution Overview
Problem
Current semiconductor devices with NMOS and PMOS transistors face challenges in optimizing transistor thickness and manufacturing processes to enhance performance and efficiency, particularly in the stacking and oxidation of channel and gate structures.
Innovation Solution
The semiconductor device incorporates NMOS and PMOS transistors with alternately stacked channel and gate structures, where NMOS channels are thinner and have thicker gates compared to PMOS channels, utilizing sacrificial layers, silicon layers, and silicon germanium layers to improve carrier mobility and manufacturing efficiency through specific oxidation and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS and PMOS transistors are manufactured with uniform thickness and structure, then manufacturing process is simplified, but transistor performance and carrier mobility cannot be optimized
Solution Approach 1:
The patent applies local quality by giving different thickness specifications to NMOS and PMOS transistors according to their specific performance requirements. NMOS transistors are designed with thinner channels while PMOS transistors have thicker channels, allowing each transistor type to be optimized for its specific carrier mobility characteristics without compromising the other
Solution Approach 2:
The manufacturing process is segmented into separate etching stages - a first etching process creates preliminary channel patterns for both NMOS and PMOS regions, then a second etching process selectively removes material to form the final different thickness structures. This segmentation allows complex differentiating features to be achieved through multiple simpler steps rather than a single complex process
2Ease of manufacture
If sacrificial layers are removed early in the manufacturing process, then subsequent processing is simplified, but channel pattern precision may be compromised
Solution Approach 1:
The sacrificial layers are removed in a preliminary action during the first etching process to create preliminary channel patterns before the second etching process forms the final channel structures. This preliminary removal simplifies subsequent processing by eliminating obstacles early, while the sacrificial layers' strategic placement ensures channel pattern precision is maintained through the staged approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of NMOS and PMOS transistors by optimizing transistor thickness and manufacturing processes, improving carrier mobility and efficiency in semiconductor devices.
Implementation Method 1
forming first silicon oxide layers and second silicon oxide layers by oxidizing surfaces of the first silicon layers and the second silicon layers
Data Source
AI summary
A semiconductor device includes an NMOS transistor structure formed over an NMOS area of a substrate; and a PMOS transistor structure formed over a PMOS area of the substrate. The NMOS transistor structure includes NMOS source/drain regions, and NMOS channel patterns and NMOS gate structures alternately and repeatedly stacked between the NMOS source/drain regions. The PMOS transistor structure includes PMOS source/drain regions, and PMOS channel patterns and PMOS gate structures alternately and repeatedly stacked between the PMOS source/drain regions.