Stacked Non-Volatile Memory Device 3D Architecture
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Solution Overview
Problem
Current non-volatile memory devices face challenges in increasing density while maintaining efficiency and cost-effectiveness, particularly in stacked nitride read-only memory designs which are rarely implemented due to incompatibility with modern fabrication processes.
Innovation Solution
A stacked non-volatile memory device is fabricated using SOI processing techniques with successive bitline and wordline layers, employing trapping structures like ONO and SONOS configurations, and efficient processing methods such as HDP-CVD and photolithography to achieve higher memory densities and cost-effective production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory device construction is implemented to increase density, then memory density is improved, but fabrication compatibility and manufacturing efficiency deteriorate
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to 3D stacked architecture by adding vertical dimension with multiple bitline layers (first bitline layer, second bitline layer) and wordline layers at different heights, separated by interlayer dielectric layers. This dimensional change enables increased storage capacity without increasing footprint area.
Solution Approach 2:
The memory device is segmented into multiple functional layers including first bitline layer, second bitline layer, first wordline layer, second wordline layer, and interlayer dielectric layers. Each layer is fabricated using separate processing steps, allowing independent optimization and compatibility with existing fabrication processes while achieving 3D stacking.
2Quantity of substance
If traditional stacked nitride read-only memory designs are used, then memory density is improved, but manufacturing cost and process efficiency worsen
Solution Approach 1:
The patent forms trapping structures (ONO or SONOS) and interlayer dielectric layers in advance before fabricating the bitline and wordline conductors. This preliminary action allows subsequent lithography and etching steps to proceed efficiently with standard processes, improving manufacturing productivity while maintaining high density.
Solution Approach 2:
The trapping structures serve multiple functions: charge storage for non-volatile memory operation, and as etch stop layers during fabrication. The interlayer dielectric layers provide both electrical isolation between conductor layers and mechanical support. This multi-functionality reduces the number of separate processing steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of highly dense memory devices with efficient fabrication processes, overcoming the inefficiencies and high costs associated with traditional stacked memory device production.
Implementation Method 1
efficient processing methods such as HDP-CVD and photolithography
Data Source
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AI summary
A stacked non-volatile memory device (100) comprises a plurality of bitline (110) and wordline (120) layers stacked on top of each other. The bitline (110) layers comprise a plurality of bitlines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.