Vertically Stacked Nonvolatile Memory Integration Density
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Solution Overview
Problem
The increasing complexity and cost of manufacturing multi-level nonvolatile memory devices due to the difficulty in fabricating and testing vertically stacked layers, which limits the integration density and operating speed of these devices.
Innovation Solution
A nonvolatile memory device design featuring alternating layers of semiconductor layers separated by isolation layers, with control gate electrodes and charge storing layers disposed on either side of the isolation layer, allowing for a vertically stacked, multi-layered structure that increases integration density while reducing manufacturing challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers in a multi-level nonvolatile memory device is increased to improve integration density, then the data storage capacity increases, but the difficulties associated with fabrication and testing increase and manufacturing costs rise
Solution Approach 1:
The memory device is divided into multiple independent stacked layers, each containing complete memory cell structures with semiconductor layers, charge storing layers, and control gate electrodes. Each layer can be independently fabricated and tested, reducing overall complexity despite increased integration density
Solution Approach 2:
The invention transitions from conventional single-level planar structures to multi-level vertically stacked architectures, utilizing the vertical dimension (Z-direction) to increase integration density while maintaining manageable fabrication processes through standardized layer stacking
2Area of stationary object
If conventional single-level devices are replaced with multi-level devices to increase integration density, then more data can be stored in the same footprint, but manufacturing costs increase due to fabrication and testing difficulties
Solution Approach 1:
Multiple memory layers are combined in a vertically stacked configuration within the same lateral footprint, allowing each layer to share common fabrication processes and testing methodologies, thereby increasing storage capacity without proportionally increasing manufacturing costs
Solution Approach 2:
The invention utilizes vertical stacking in the Z-direction to maximize lateral footprint utilization, enabling multiple memory cells to occupy the same planar area through layered construction, thus improving area efficiency while maintaining manufacturing feasibility
Data Source
AI summary
A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.