Stacked Non-Volatile Memory Device With Intersecting Electrodes

The patent transitions from conventional planar single-layer memory structures to a three-dimensional stacked multi-layer architecture. Memory cells are arranged vertically across multiple layers, with word lines extending in the first direction and bit lines in the second direction, creating a spatial matrix that dramatically increases storage capacity within the same footprint. This dimensional transformation allows efficient addressing and selection of individual cells through the layer stack.

The memory device is divided into multiple discrete layers, each containing arrays of memory cells formed by intersecting word lines and bit lines. Each layer can be independently addressed and accessed, allowing parallel operation and reducing the complexity of any single layer while maintaining high overall capacity. The segmented structure enables modular manufacturing and testing.

Semiconductor layers are formed to extend beyond the edges of the first electrode in advance, creating preliminary contact regions that simplify subsequent fabrication steps. This preliminary extension ensures proper electrical connections are established before final assembly, reducing manufacturing complexity despite the multi-layer structure.

The patent employs a nested structure where semiconductor layers are positioned within and around electrode structures across multiple layers. The semiconductor layers extend from lower layers into upper layers, creating integrated contact regions that are embedded within the stacked architecture. This nesting approach consolidates multiple functions into unified structures, simplifying the manufacturing process.