Stacked OLED Pixel Transistor Layout for High-Resolution Displays
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Solution Overview
Problem
Current display devices face challenges in achieving high resolution due to limitations in integrating semiconductor elements for driving light emitting elements effectively.
Innovation Solution
The proposed solution involves a display device architecture with multiple transistors and a capacitor, where transistors are disposed on different layers, and semiconductor patterns are made of polycrystalline silicon, with specific insulating and conductive layers to enhance the integration and performance of semiconductor elements for driving organic light emitting diodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple transistors are integrated on the same layer to drive light emitting elements, then the integration density increases, but the manufacturing complexity and difficulty of achieving high resolution worsen
Solution Approach 1:
The patent applies three-dimensional stacking of transistor layers to increase integration density. Multiple transistor layers (first transistor layer, second transistor layer, third transistor layer) are vertically stacked above each other, allowing more semiconductor elements to be integrated within the same planar footprint without proportionally increasing manufacturing complexity. This vertical arrangement enables high-resolution displays by packing more driving elements into limited pixel areas.
2Manufacturing precision
If transistors are disposed on different layers to achieve high resolution, then the integration of semiconductor elements improves, but the device structure complexity increases
Solution Approach 1:
The patent implements nested transistor structures where smaller transistors are positioned within or adjacent to larger transistors across different layers. For example, second transistors are disposed within regions defined by first transistors, and third transistors are integrated within regions defined by second transistors. This nesting approach maximizes space utilization and achieves high resolution while managing structural complexity through hierarchical organization.
Solution Approach 2:
The patent resolves structure complexity by transitioning from two-dimensional planar arrangements to three-dimensional stacked configurations. Multiple transistor layers are vertically arranged with precise spatial relationships, allowing high-resolution pixel designs without proportionally increasing lateral structure complexity. The vertical stacking enables compact integration of numerous transistors needed for high-resolution displays.
3Manufacturing precision
If the area required for each pixel is reduced to enhance display performance, then the resolution improves, but the space for semiconductor elements becomes limited
Solution Approach 1:
The patent overcomes pixel area limitations by stacking transistor layers vertically. Multiple transistor layers (first, second, and third transistor layers) are arranged above each other within the confined pixel area, enabling sufficient semiconductor element integration despite reduced lateral space. This vertical expansion allows high-resolution displays with adequate driving elements in compact pixels.
Solution Approach 2:
The patent nests smaller transistors within the spatial envelope of larger transistors across different layers. Second transistors are positioned within regions defined by first transistors, and third transistors are integrated within regions defined by second transistors. This nested arrangement maximizes the utilization of limited pixel area while providing sufficient space for all necessary semiconductor elements to achieve high resolution.
Data Source
AI summary
A display device includes an organic light emitting diode, a first transistor driving the organic light emitting diode, a second transistor transmitting a data signal to the first transistor, a third transistor transmitting a first power voltage to the first transistor, wherein a semiconductor pattern of the first transistor is disposed over a semiconductor pattern of the second transistor, a semiconductor pattern of the third transistor is disposed over the semiconductor pattern of the first transistor, a lower transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the second transistor, and an upper transistor insulating film is disposed between the semiconductor pattern of the first transistor and the semiconductor pattern of the third transistor.