3D Stacked Optical Device Backside Contact Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current optical packaging solutions face challenges in achieving high channel density and communication speeds due to operational surfaces and electrical contacts being on the same side, limiting the ability to meet increasing bandwidth requirements for future electronic devices.
Innovation Solution
A method involving the mounting of optical devices on a transparent substrate, forming vias, filling them with conductive material to create backside contacts, and integrating an electronic chip with corresponding backside contacts to enable a three-dimensional stacked optical device that allows light transmission while facilitating high-speed communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If electrical contacts and operational surfaces are placed on the same side of the optical device, then the device structure is simplified, but the packaging density and communication bandwidth are limited
Solution Approach 1:
The patent transitions from a two-dimensional planar layout where all contacts and operational surfaces are on the same side to a three-dimensional stacked architecture. Electrical contacts are moved to the backside of the optical device, enabling vertical stacking of multiple optical devices and electronic chips. This dimensional change increases packaging density and allows higher communication bandwidth while maintaining structural organization.
2Ease of manufacture
If electrical contacts and operational surfaces are placed on the same side of the optical device, then manufacturing is easier, but communication bandwidth and channel density cannot meet future requirements
Solution Approach 1:
The optical device is segmented into distinct functional regions: operational surfaces on the front side for light emission/detection and electrical contacts on the backside for signal transmission. This segmentation allows independent optimization of optical and electrical functions, enabling higher channel density and communication bandwidth while maintaining manufacturing feasibility through standardized backside contact arrays.
Solution Approach 2:
By moving electrical contacts to the backside and enabling vertical stacking in the third dimension, the system achieves higher communication bandwidth and channel density without compromising manufacturing ease. The standardized backside contact configuration maintains manufacturing simplicity while the 3D stacking architecture enables future-proof bandwidth scalability.
3Area of stationary object
If multiple channels are integrated in a planar configuration, then device area is minimized, but bandwidth requirements cannot be met
Solution Approach 1:
The patent resolves the bandwidth-area contradiction by transitioning from planar to three-dimensional stacking. Multiple optical devices and electronic chips are vertically stacked with backside contacts enabling inter-layer connections. This vertical integration achieves high channel density and terabyte/second bandwidth while minimizing the footprint device area, as the expanded capacity is achieved in the vertical dimension rather than lateral expansion.
Data Source
AI summary
A method of forming a three-dimensional stacked optical device includes mounting at least one optical device to a transparent substrate, fabricating a plurality of vias though the at least one optical device, and filling the plurality of vias with a conductive material member that forms a plurality of backside contacts on the at least one optical device. The method further requires mounting an electronic chip to the plurality of backside contacts on the at least one optical device, fabricating a plurality of vias in the electronic chip, filling each of the plurality of vias in the electronic chip with a another conductive material member, and depositing a backside contact at each of the plurality of vias formed in the electronic chip. Each backside contact is electrically connected to corresponding ones of the another conductive material member positioned in respective ones of the plurality of vias formed in the electronic chip.