Stacked Optical Package Layout for Shorter Signal Paths
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Solution Overview
Problem
In silicon photonics and optical engines with integrated electronic ICs and photonic ICs, the long transmission path between components leads to signal distortion and increased device area, complicating manufacturing and increasing costs.
Innovation Solution
The optical device design includes a processing component, electronic components, pillars, and encapsulants, with vertical electrical connections and reduced pitch between components, reducing transmission path length and eliminating the need for additional connection elements, thereby improving electrical performance and simplifying manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electronic ICs are arranged side-by-side with ASIC in a package, then electrical connection is achieved, but transmission path length increases leading to signal distortion and increased device area
Solution Approach 1:
The patent transitions from a planar side-by-side arrangement to a three-dimensional stacked architecture where electronic ICs are positioned vertically above the ASIC substrate. This vertical stacking enables direct electrical connection through pillars and conductive structures, dramatically shortening the transmission path while maintaining reliable electrical connectivity between components.
Solution Approach 2:
The patent implements a nested structure where electronic ICs are placed within the vertical space above the ASIC substrate, utilizing the Z-dimension for component placement. This nesting approach allows multiple components to occupy overlapping horizontal footprints while maintaining short transmission paths through vertical interconnects.
2Reliability
If electronic ICs are arranged side-by-side with ASIC in a package, then electrical connection is achieved, but device area increases complicating manufacturing and increasing costs
Solution Approach 1:
By moving from two-dimensional lateral arrangement to three-dimensional vertical stacking, the patent reduces the horizontal footprint required for multiple components. The electronic ICs occupy vertical space above the ASIC rather than extending the device area laterally, thereby reducing overall device area and simplifying manufacturing.
Solution Approach 2:
The nested vertical arrangement allows components to share horizontal space, with electronic ICs positioned above the ASIC substrate in a stacked configuration. This nesting reduces the total device area required compared to side-by-side placement while maintaining all necessary electrical connections.
3Reliability
If additional connection elements are used to connect electronic ICs to ASIC, then electrical connection is achieved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the connection function into integrated pillar structures that directly connect electronic ICs to the ASIC substrate. These pillars combine mechanical support and electrical conduction in a single unified structure, eliminating the need for separate connection elements and reducing device complexity.
Solution Approach 2:
The pillar structures serve multiple functions simultaneously: providing mechanical support for the electronic ICs, establishing electrical connection between layers, and enabling signal transmission. This multi-functionality reduces the number of discrete components needed and simplifies the overall device architecture.
Data Source
AI summary
An optical device is provided. The optical device includes a processing component, a first electronic component, a second electronic component, a first pillar, and an encapsulant. The first electronic component is disposed over and electrically connected to the processing component. The second electronic component is disposed over the processing component and electrically connected to the first electronic component. The first pillar is disposed between the first electronic component and the second electronic component and electrically connected to the processing component. The encapsulant is disposed over the processing component. The encapsulant encapsulates the first electronic component, the second electronic component, and the first pillar.