3D Stacked Optical Transceiver for Single-Photon Detector Integration
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Solution Overview
Problem
Existing integrated optical transceivers face challenges in integrating driving and control functions with single-photon detectors on a single silicon chip due to diverse requirements of optoelectronics, high-voltage drive components, and high-speed logic, making it difficult to reduce chip area and cost for mass-market applications.
Innovation Solution
A three-layer semiconductor die structure is used, comprising a silicon die with avalanche photodetectors, a silicon die with high-voltage circuits, and a silicon die with low-voltage logic circuits, bonded together to integrate emitter and detector functions, sharing circuit elements like phase-locked loops and reducing inter-die interface complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all driving and control functions are integrated on a single silicon chip with single-photon detectors, then device functionality is improved, but manufacturing complexity and cost increase due to diverse requirements of optoelectronics, high-voltage drive components, and high-speed logic
Solution Approach 1:
The device is divided into three separate semiconductor dies: a first die containing single-photon detectors, a second die containing high-voltage drive circuits, and a third die containing low-voltage logic circuits. This segmentation allows each die to be optimized for its specific function while reducing the manufacturing complexity of integrating all functions on a single chip.
Solution Approach 2:
The solution transitions from planar integration on a single chip to three-dimensional stacking of multiple dies. The dies are bonded together in a vertical configuration, utilizing the third dimension (depth) to achieve integration without the manufacturing complexity of monolithic integration.
2Device complexity
If separate chips are used for detectors and driving/control functions, then manufacturing complexity is reduced, but chip area and inter-die interface complexity increase
Solution Approach 1:
Multiple functional dies are stacked vertically and bonded together, transitioning from a planar layout to a three-dimensional structure. This reduces the overall chip area footprint while maintaining separate manufacturing processes for each die type.
Solution Approach 2:
The solution merges multiple separate chips into a single integrated package through die stacking and bonding. The detector die, high-voltage driver die, and logic die are physically combined in a compact three-dimensional structure, reducing the total area occupied by separate components.
3Area of stationary object
If monolithic integration is attempted on a single chip, then chip area is reduced, but manufacturing difficulty increases due to incompatible process requirements
Solution Approach 1:
The device is segmented into multiple dies that can be manufactured using different semiconductor fabrication processes optimized for each function (detector fabrication, high-voltage circuit fabrication, logic circuit fabrication). This avoids the manufacturing difficulties of monolithic integration while achieving area reduction through stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip area and cost by eliminating inter-die interface circuits, sharing pads and high-speed analog/digital circuits, and enabling efficient integration of high-voltage driving and high-speed logic functions, suitable for mass-market applications.
Implementation Method 1
at least one avalanche photodetector configured to output electrical pulses in response to photons incident on the first front surface
Implementation Method 2
the optical emitter includes a vertical-cavity surface-emitting laser (VCSEL)
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
An optoelectronic device (20) includes a first semiconductor die (22), having first front and rear surfaces (32, 34) and including at least one avalanche photodetector (28) configured to output electrical pulses in response to photons incident on the first front surface. A second semiconductor die (24) has a second front surface (36), which is bonded to the first rear surface, and a second rear surface (40), and includes a photodetector receiver analog circuit (48) coupled to the at least one avalanche photodetector and an emitter driver circuit (50) configured to drive a pulsed optical emitter (52). A third semiconductor die (26) has a third front surface (42), which is bonded to the second rear surface, and a third rear surface, and includes logic circuits (60, 62, 64) coupled to control the photodetector receiver analog circuit and the emitter driver circuit and to receive and process the electrical pulses output by the at least one avalanche photodetector.