Stacked Optical Transceiver Architecture for Single-Chip ToF Sensing
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Solution Overview
Problem
Existing technologies face challenges in integrating driving and control functions with single-photon detectors on a single silicon chip for direct time-of-flight depth sensors, due to the diverse requirements of optoelectronics, high-voltage drive components, and high-speed logic, which complicates chip area and reduces efficiency.
Innovation Solution
A three-layer semiconductor die structure is used, comprising a silicon die with avalanche photodetectors, a silicon die with high-voltage circuits, and a silicon die with low-voltage logic circuits, bonded together to form an integrated optical transceiver, sharing circuit elements and reducing the overall chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all driving and control functions are integrated on a single silicon chip with single-photon detectors, then device integration is improved, but chip area and complexity increase due to diverse requirements of optoelectronics, high-voltage drive components, and high-speed logic
Solution Approach 1:
The device is divided into three separate semiconductor dies stacked vertically: first die containing avalanche photodetectors, second die containing high-voltage drive circuits, and third die containing low-voltage logic circuits. This segmentation allows each die to be optimized for its specific function while reducing the overall chip area compared to a single integrated chip.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture. By bonding multiple dies vertically together, the system achieves high integration without increasing the lateral chip area, effectively utilizing the vertical dimension to resolve the contradiction between integration and area.
2Device complexity
If separate chips are used for detectors, drive circuits, and logic circuits, then chip area is reduced, but device complexity and pad count increase
Solution Approach 1:
Multiple functional dies are merged into a single stacked device through direct bonding. The first die with photodetectors, second die with drive circuits, and third die with logic circuits are bonded together to form an integrated assembly that functions as a unified device with reduced pad count and simplified external connections.
Solution Approach 2:
The patent implements a nested structure where multiple functional units are contained within a compact stacked arrangement. Each die is nested vertically above the other, creating a space-efficient configuration that maintains full functionality while minimizing the overall device footprint.
3Adaptability or versatility
If high-voltage drive circuits and low-voltage logic circuits are integrated on the same die, then device integration is improved, but manufacturing complexity increases due to diverse voltage requirements
Solution Approach 1:
The patent separates high-voltage drive circuits and low-voltage logic circuits onto different semiconductor dies. This segmentation allows each die to be manufactured using optimized processes for its voltage requirements, simplifying manufacturing while maintaining functional integration through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a compact, efficient integration of emitter and detector functions, reducing chip area, complexity, and pad count, while enabling high-voltage driving and high-speed logic operations, suitable for mass-market applications.
Implementation Method 1
at least one avalanche photodetector configured to output electrical pulses in response to photons incident on the first front surface
Implementation Method 2
the first rear surface is bonded to the second front surface by an oxide bond
Implementation Method 3
the second rear surface and the third front surface include respective metal pads and are bonded together by hybrid bonding between the respective metal pads
Data Source
AI summary
An optoelectronic device includes a first semiconductor die, having first front and rear surfaces and including at least one avalanche photodetector configured to output electrical pulses in response to photons incident on the first front surface. A second semiconductor die has a second front surface, which is bonded to the first rear surface, and a second rear surface, and includes a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and an emitter driver circuit configured to drive a pulsed optical emitter. A third semiconductor die has a third front surface, which is bonded to the second rear surface, and a third rear surface, and includes logic circuits coupled to control the photodetector receiver analog circuit and the emitter driver circuit and to receive and process the electrical pulses output by the at least one avalanche photodetector.