Stacked Si and Oxide CMOS Structure for Stable Low-Power Logic
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Solution Overview
Problem
Existing semiconductor devices face challenges in circuit area reduction, stable operation with respect to temperature changes, and power consumption due to the use of complementary logic circuits with Si and OS transistors, which have different electrical characteristics and require complex manufacturing processes.
Innovation Solution
A semiconductor device is designed with a p-channel transistor over a silicon substrate and an n-channel transistor using a metal oxide, where the transistors share a common connection and have separate back gate electrodes to control threshold voltage, allowing for reduced circuit area and stable operation across temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a complementary logic circuit is formed using Si and OS transistors, then the device can achieve logic circuit functionality, but the circuit area increases and manufacturing process becomes complicated due to different electrical characteristics requiring separate formation processes
Solution Approach 1:
The patent combines Si and OS transistors into a single integrated structure where the Si transistor is formed in a silicon layer and the OS transistor is formed in a metal oxide semiconductor layer above it. Both transistors share common structures such as the gate electrode, gate insulating layer, and source/drain regions, allowing them to be manufactured together in a unified process rather than separately
Solution Approach 2:
The gate electrode and gate insulating layer serve dual functions by acting as the gate structure for both the Si transistor and the OS transistor. Similarly, the source and drain regions function as electrodes for both transistors, eliminating the need for separate gate and electrode formation processes for each transistor type
2Use of energy by moving object
If back gates are provided for controlling threshold voltage in Si transistors, then low-voltage driving is achieved, but the number of electrodes increases and circuit area increases
Solution Approach 1:
The back gate electrode is shared between the Si transistor and the OS transistor. The same electrode that serves as the back gate for the Si transistor also functions as the gate electrode for the OS transistor, eliminating the need for separate back gate electrodes and reducing the total number of electrodes required
3Power
If OS transistor size is increased to match Si transistor on-state current, then current balance is achieved, but the transistor size becomes unbalanced and circuit area increases
Solution Approach 1:
The patent applies different material properties locally to achieve current balance without size matching. The Si transistor utilizes the high mobility of silicon carriers, while the OS transistor utilizes the low off-state current characteristics of metal oxide semiconductor. This allows each transistor to operate at its optimal current level with appropriately sized channels, avoiding the need to oversized the OS transistor
4Adaptability or versatility
If Si and OS transistors are used together, then device functionality is enhanced, but stable operation with respect to temperature changes becomes difficult due to different electrical characteristics
Solution Approach 1:
The back gate electrode provides a feedback mechanism for threshold voltage control. By adjusting the potential applied to the back gate electrode, the threshold voltages of both the Si transistor and OS transistor can be dynamically controlled to compensate for temperature-induced variations, ensuring stable operation across different temperature conditions
Data Source
AI summary
A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.