Stacked Oxide Semiconductor Memory Cells for Dense Reliable Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, circuit area reduction, improved operating speed, write and read speed, low power consumption, reliability, and favorable electrical characteristics, particularly in integrating high-density miniaturized transistors for advanced electronic devices.
Innovation Solution
A semiconductor device is designed with multiple sub-memory cells, each comprising a first and second transistor and a capacitor, using oxide semiconductor layers, where the semiconductor layers are stacked and connected in a specific configuration to optimize electrical connections and reduce circuit area, with In, M, and Zn-based oxide semiconductors having specific atomic ratios to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to increase integration density, then productivity and integration density improve, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent transitions from planar transistor arrangement to a three-dimensional stacked configuration where multiple transistor layers are vertically integrated. This dimensional change allows higher integration density without further miniaturizing individual transistors, thereby maintaining manufacturing precision while improving productivity through increased spatial utilization.
Solution Approach 2:
The invention divides the semiconductor device into multiple distinct layers, each containing transistors with specific functions. This segmentation allows each layer to be optimized independently for its intended purpose, with through-silicon vias providing controlled interconnections, thus maintaining manufacturing precision while achieving high integration density through vertical stacking.
2Area of stationary object
If circuit area is reduced for compact devices, then device size decreases, but manufacturing precision and electrical characteristics worsen
Solution Approach 1:
The patent reduces circuit area by stacking transistor layers vertically in the third dimension rather than packing them horizontally. This approach maintains adequate spacing and manufacturing precision within each layer while achieving compact overall device dimensions through vertical integration, thus reducing footprint without sacrificing fabrication quality.
3Productivity
If transistors are miniaturized for high-density integration, then integration density improves, but operating speed deteriorates
Solution Approach 1:
The patent maintains larger transistor dimensions within each layer to preserve operating speed, while achieving high integration density through vertical stacking of multiple layers. The through-silicon via interconnections enable efficient signal routing between layers, ensuring that operating speed is not compromised by the increased integration density achieved through three-dimensional architecture.
Data Source
AI summary
[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.