Stacked Oxide Semiconductor Layers for Transistor Integration
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Solution Overview
Problem
Miniaturization of transistors leads to deterioration of electrical characteristics, such as on-state current, threshold voltage, and subthreshold value, making it challenging to achieve high integration, low power consumption, and reliable semiconductor devices that can retain data even without a power supply.
Innovation Solution
A semiconductor device with stacked oxide semiconductor layers, where the second oxide semiconductor layer is smaller than the first, and a third oxide semiconductor layer is in contact with the source and drain electrode layers, reducing interface states and carrier scattering, and maintaining a continuous energy band structure to enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor miniaturization is implemented to achieve high integration, then device integration density is improved, but electrical characteristics such as on-state current, threshold voltage, and subthreshold value deteriorate
Solution Approach 1:
The invention transitions from a conventional single-layer semiconductor structure to a stacked multi-layer oxide semiconductor structure. By adding vertical dimensionality with multiple oxide semiconductor layers (first, second, and third oxide semiconductor layers), the device maintains improved integration density while recovering electrical characteristics through the enhanced structural configuration.
Solution Approach 2:
The invention employs composite oxide semiconductor materials with different compositions and properties in each layer. The first oxide semiconductor layer, second oxide semiconductor layer, and third oxide semiconductor layer are composed of different materials optimized for specific functions, creating a composite structure that simultaneously achieves high integration and maintains superior electrical characteristics.
2Area of moving object
If transistor size is reduced for miniaturization, then area occupation is decreased, but on-state current characteristics deteriorate
Solution Approach 1:
By stacking multiple oxide semiconductor layers vertically, the invention compensates for the reduced horizontal area of miniaturized transistors. The vertical stacking provides additional conduction pathways and increases the effective channel area, thereby maintaining on-state current characteristics despite the reduced transistor footprint.
Solution Approach 2:
The invention nests multiple oxide semiconductor layers within each other in a vertical stack configuration. The first oxide semiconductor layer is positioned at the bottom, followed by the second oxide semiconductor layer, and the third oxide semiconductor layer at the top, creating a nested structure that maximizes the use of vertical space to maintain electrical performance in miniaturized devices.
Data Source
AI summary
Provided is a semiconductor device in which deterioration of electrical characteristics can be suppressed. The semiconductor device includes a first oxide semiconductor layer over an insulating surface, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer whose one surfaces are in contact with part of the first oxide semiconductor layer and part of the second oxide semiconductor layer, a third oxide semiconductor layer over the first oxide semiconductor layer and the second oxide semiconductor layer, a gate insulating film over the third oxide semiconductor layer, and a gate electrode layer over the gate insulating film. The second oxide semiconductor layer wholly overlaps with the first oxide semiconductor layer. Part of the third oxide semiconductor layer is in contact with the other surfaces of the source electrode layer and the drain electrode layer.